參數(shù)資料
型號(hào): ZL50031
廠商: Zarlink Semiconductor Inc.
英文描述: Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch
中文描述: 靈活的為4 K × 2鉀通道數(shù)字交換機(jī)的H.110接口和2度x 2度本地交換
文件頁數(shù): 65/74頁
文件大?。?/td> 765K
代理商: ZL50031
ZL50031
Data Sheet
65
Zarlink Semiconductor Inc.
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
* Note 1: To meet the H.110 output timing requirement, the output delay time can be reduced further by programming the backplane output
advancement registers (BOA0 - 3).
* Note 2: High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel the time taken to discharge C
L
.
Figure 30 - Backplane Serial Stream Timing when the Data Rate is 8 Mbps
AC Electrical Characteristics
- Backplane Serial Streams with Date Rate of 8 Mbps
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
BSTio0-31 Input Data Sample Point
t
SAMP8
t
CIS8
t
CIH8
t
DOD8
91.5
91.5
91.5
ns
2
BSTio0-31 Input Setup Time
12.5
ns
3
BSTio0-31 Input Hold Time
12.5
ns
4
BSTio0-31 Output Delay
Active to Active
-6.5
12.5
ns
C
L
= 30 pF, Note 1
5
Per Channel boundary HiZ
t
DOZ8
t
ZDO8
10
10
ns
ns
R
L
=1 K, C
L
=30 pF,
Note 2
FRAME_A_io,
FRAME_B_io
(INPUT)
C8_A_io,
C8_B_io
(8.192 MHz)
(INPUT)
BSTio (8 Mbps)
Backplane input
BSTio (8 Mbps)
Backplane output
V
TT
Bit 1
Ch 0
Bit 2
Ch 0
Bit 3
Ch 0
Bit 4
Ch 0
Bit 7
Ch127
Bit 6
Ch127
Bit 0
Ch 0
t
CIS8
V
TT
Bit 4
Ch 0
Bit 3
Ch 0
Bit 2
Ch 0
Bit 1
Ch 0
Bit 0
Ch 0
Bit 7
Ch127
Bit 6
Ch127
t
DOZ8
t
DOD8
t
CIH8
t
SAMP8
t
ZDO8
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