參數(shù)資料
型號(hào)： TNET3001
廠商： Texas Instruments, Inc.
英文描述： SONET STS-1 Overhead Terminator(SONET STS-1附加終端)
中文描述： SONET的STS - 1的開(kāi)銷終結(jié)者（SONET的STS - 1的附加終端）
文件頁(yè)數(shù)： 8/49頁(yè)
文件大?。?/td> 1090K
代理商： TNET3001
TNETS3001
SONET STS-1 OVERHEAD TERMINATOR
SDNS007B – OCTOBER 1993 – REVISED JUNE 1995
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
alarm-indication ports
TERMINAL
NAME
I/O
DESCRIPTION
NO.
RAIS
11
O
TTL
Receive alarm-indication signal. RAIS is an active-low signal indicating that a downstream AIS must be
generated. RAIS is activated when PTE =1 or LTE =1 and any of the following conditions are active: RLOC,
RLOS, RLOF, RLAIS, RLOP, RPAIS.
TAIS
35
I
TTL
Transmit alarm-indication signal. TAIS is an active-low input that causes AIS to be introduced into the transmit
line.
phase-lock loop
TERMINAL
NAME
I/O
DESCRIPTION
NO.
TCAP
57
I/O
External resistor capacitor. TCAP is a 1.2-k
, 1/4 W, 5% carbon composition resistor in series with a 1000-pF
capacitor connected to analog ground. The RC network is required when the terminal interface is used in the
following modes: parallel and SPE only.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
(see Note 1)
Input voltage range, V
I
Operating free-air temperature range, T
A
Operating junction temperature
Storage temperature range, T
stg
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
–0.3 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–0.5 V to V
CC
+ 0.5 V
–40
°
C to 85
°
C
150
°
C
–55
°
C to 150
°
C
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
AVCC
Supply voltage
4.75
5
5.25
V
Supply voltage, analog
4.75
5
5.25
V
VIH
Hi h l
High-level input voltage
CMOS
3.15
V
CMOS (see Note 2)
2
TTL
2
TTL (see Note 3)
2
VIL
Low-level input voltage
CMOS
1.65
V
CMOS (see Note 2)
0.8
TTL
TTL (see Note 3)
0.8
0.8
NOTES:
2. Input has a 100-k
internal pullup resistor.
3. Input has a 9-k
internal pullup resistor.
P
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