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| 型號： | TNET3001 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET STS-1 Overhead Terminator(SONET STS-1附加終端) |
| 中文描述： | SONET的STS - 1的開銷終結(jié)者（SONET的STS - 1的附加終端） |
| 文件頁數(shù)： | 32/49頁 |
| 文件大小： | 1090K |
| 代理商： | TNET3001 |
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TNETS3001
SONET STS-1 OVERHEAD TERMINATOR
SDNS007B – OCTOBER 1993 – REVISED JUNE 1995
32
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
status register 0 (see Notes 19, 20, and 21)
0F0, 0F1,
0F4
BIT
7
SYMBOL
RLOC
NAME
Receive loss of clock
200 ns of no transitions in receive-line
clock RLCI
BIT
SYMBOL
NAME
Any transition of the receive-line
clock RLCI
0F0, 0F1
6
RNPTR
Receive new pointer
A new-pointer value due to new-data flag
or three consecutive frames of different
pointer values
Microprocessor read from address
0F0 or writing 1 to bit 6 of address
0F2
0F0, 0F1,
0F4
5
RPAIS
Receive path AIS
Three consecutive frames of all ones in
H1 and H2 bytes
NDF with valid pointer or three
successive frames with valid
pointer
0F0, 0F1,
0F4
4
RLAIS
Receive line AIS
Five consecutive frames of 111 in the bits
2,1,0 (6,7,8 transmission-bit standard) of
the K2 byte
Five consecutive frames of
patterns other than 111 in the
bits 2,1,0 (6,7,8 transmission-bit
standard) of the K2 byte
0F0, 0F1,
0F4
3
RLOP
Receive loss of pointer
Eight consecutive frames of invalid
pointer or NDF
Three consecutive frames of valid
pointer
0F0, 0F1,
0F4
2
RLOF
Receive loss of frame
Eight consecutive frames of out-of-frame
condition
Eight consecutive frames of
in-frame condition
0F0, 0F1,
0F4
1
ROOF
Receive out of frame
Failure to acquire valid framing pattern
for four consecutive frames
Valid framing pattern exactly 6480
bits apart
0F0, 0F1,
0F4
0
RLOS
Receive loss of signal
STS-1 mode. 20
μ
s of all zeros in the
scrambled data RLDI or RXLOS low.
STS-N mode. 6480 bits of all zeros or all
ones or RXLOS low.
STS-1 mode. A valid framing
pattern in the scrambled data and
RXLOS high.
STS-N mode. Any transition in
RLDI and RXLOS high.
NOTES: 19. The address 0F0 contains latched values of these status bits, which reset on read.
20. The address 0F1 contains latched values of these status bits, but do not reset on read. Write one to an individual bit to reset. Write
back read value to reset the entire register.
21. The address 0F4 contains unlatched values of these status bits. The information is transient.
P
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