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參數(shù)資料
| 型號： | TNET3001 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET STS-1 Overhead Terminator(SONET STS-1附加終端) |
| 中文描述： | SONET的STS - 1的開銷終結(jié)者（SONET的STS - 1的附加終端） |
| 文件頁數(shù)： | 5/49頁 |
| 文件大?。?/td> | 1090K |
| 代理商： | TNET3001 |
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TNETS3001
SONET STS-1 OVERHEAD TERMINATOR
SDNS007B – OCTOBER 1993 – REVISED JUNE 1995
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
power supply
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AGND
56
O
Analog ground
Analog supply voltage, 5 V
±
5%
Digital ground
Supply voltage, 5 V
±
5%
AVCC
GND
58
I
5, 14, 24, 62, 68, 78
O
VCC
1, 17, 28, 47, 69
I
microprocessor interface
TERMINAL
NAME
I/O
DESCRIPTION
NO.
A8
22
I
Address bus This is bit 8 of the address bus
Address bus. This is bit 8 of the address bus.
TTL
AD7–AD4
AD3–AD2
AD1–AD0
21–18
16–15
13–12
I/O
TTL
Address/data bus. These signals provide the time-multiplexed address and data interface between the
microprocessor and internal RAM.
ALE
32
I
TTL
Address latch enable. ALE is an active-high signal provided by the microprocessor that latches the address
into a TNETS3001 address latch for a bus cycle.
INT
33
O
TTL
Interrupt. INT is an active-high signal that confirms an interrupt request to the microprocessor. The hardware
interrupt request is enabled by HINT = 1 (bit 5, address 0FA).
RD
25
I
TTL
Read. RD is an active-low input generated by the microprocessor for reading the TNETS3001.
RDY
31
O
Ready. RDY is an active-high acknowledgment from the TNETS3001 that indicates a transfer can be
completed. RDY goes low when the address being read or written to corresponds to a RAM location. When
status or control registers are accessed, RDY remains high. RDY is an open-drain output capable of sinking
a maximum of 16 mA. The value of the pullup resistor depends on the number of devices that use the RDY
signal in the system.
RST
63
I
TTL
Reset. RST resets all internal counters and sets all alarms. RST is a positive pulse with a minimum width of
300 ns. RST must be used after power is applied, registers are initialized, and the clocks are stable.
SEL
34
I
TTL
Select. SEL is an active-low signal that enables data transfers between the microprocessor and TNETS3001
RAM during a read/write bus cycle.
WR
23
I
TTL
Write. WR is an active-low signal generated by the microprocessor for writing to the TNETS3001.
P
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