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| 型號： | TNET3001 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET STS-1 Overhead Terminator(SONET STS-1附加終端) |
| 中文描述： | SONET的STS - 1的開銷終結(jié)者（SONET的STS - 1的附加終端） |
| 文件頁數(shù)： | 1/49頁 |
| 文件大?。?/td> | 1090K |
| 代理商： | TNET3001 |
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TNETS3001
SONET STS-1 OVERHEAD TERMINATOR
SDNS007B – OCTOBER 1993 – REVISED JUNE 1995
Copyright
1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Provides SONET Interface to Any Type of
Payload
Programmable STS-1 or STS-N Modes
Receives Bit-Serial STS-1 Signals to Line
Side Using External Reference Frame-Pulse
Input for STS-N Applications
Transmits Bit-Serial STS-1 Signals
From Line Side Using External
Reference Frame Pulse for Outgoing
Phase Synchronization
Transmits Bit-Serial STS-1 Signals From
Line Side Using External Reference Frame
Pulse for Outgoing Phase Synchronization
Programmable Full STS-1 or SPE-Only I/O
on Terminal Side
Bit-Serial or Byte-Parallel I/O on Terminal
Side
Optional AIS Communication With Another
TNETS3001 or TNETS3003
Interface to Microprocessors With
Hierarchical Scan and Optional Hardware
Interrupt on Alarms
SONET Alarm Processing Performance
Monitoring
Meets 1991 ANSI/Bellcore Standards:
– T1X1.5/90-025R1
– TA-NWT-000253
description
The TNETS3001, synchronous optical network (SONET) overhead terminator, performs section overhead, line
overhead, and path overhead signal processing at the STS-1 (51.84 Mbit/s) data rate. Repeaters, line-
termination points, and path termination points are just a few applications that use the versatile TNETS3001.
The TNETS3001 contains three status registers, seven control registers, transport overhead RAM, and path
overhead RAM; a line-side interface, terminal-side interface, orderwire/APS interface, datacom interface, and
microprocessor interface are also integrated into a single 84-pin plastic chip carrier, which is suitable for socket
or surface mounting. Status and control registers configure the device and allow for different line-side and
terminal-side clock rates (receive/transmit pointer is recalculated as necessary to compensate for the clock
differences); the registers also enable the overhead terminator to perform loopback and serial/parallel inputs
or outputs. All transport and path overhead bytes are stored in the device RAM. Depending on the application,
new overhead bytes are substituted from RAM to either terminal or line side. Besides software and hardware
interrupts, alarm detection and alarm-indication signal (AIS) generation are provided. The device is controlled
via a 9-bit address bus and an 8-bit interleaved data bus.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
P
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