參數(shù)資料
型號: 28F1604C3
廠商: Intel Corp.
英文描述: 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲器和靜態(tài)存儲器)
中文描述: 3伏高級堆疊芯片級封裝存儲器(3V的閃速存儲器和靜態(tài)存儲器)
文件頁數(shù): 11/64頁
文件大?。?/td> 927K
代理商: 28F1604C3
28F1602C3, 28F1604C3, 28F3204C3
Preliminary
5
2.0
Principles of Operation
The flash memory utilizes a CUI and automated algorithms to simplify program and erase
operations. The WSM automates program and erase operations by handling data and address
latches, WE#, and system status requests.
.
2.1
Bus Operation
All bus cycles to or from the Stacked-CSP conform to standard microcontroller bus cycles. Four
control signals dictate the data flow in and out of the flash component: F-CE#, F-OE#, F-WE# and
F-RP#. Four separate control signals handle the data flow in and out of the SRAM component:
S-CS
1
#, S-CS
2
, S-OE#, and S-WE#. These bus operations are summarized in
Table 2
and
Table 3
.
2.1.1
Read
The flash memory has four read modes: read array, read identifier, read status and read query.
These flash memory read modes are not dependent on the F-V
PP
voltage. Upon initial device
power
-
up or after exit from reset, the flash device automatically defaults to read array mode. F-
CE# and F-OE# must be driven active to obtain data from the flash component.
The SRAM has one read mode available. S-CS
1
#, S-CS
2
, and S-OE# must be driven active to
obtain data from the SRAM device. See
Table 3, “Recommended Memory System Operating
Mode Summary” on page 6
for a summary of operations.
Figure 2. 3 Volt Advanced+ Stacked Chip Scale Package Block Diagram
1,048,576 x16 bit (16 Mbit)
2,097,152 x16 bit (32 Mbit)
3 Volt Advanced+ Boot Block
Flash Memory
131,072 x16 bit (2 Mbit)
262,144 x16 bit (4 Mbit)
SRAM
F-CE#
F-OE#
F-WE#
F-RP#
F-WP#
A
17-19
/A
18-20
A
0-16
/A
0-17
S-CS
1
#
S-CS
2
S-OE#
S-WE#
S-UB#
S-LB#
DQ
0-15
S-V
CC
S-GND
F-V
PP
F-V
CC
F-GND
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