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參數(shù)資料
| 型號： | 28F1604C3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲器和靜態(tài)存儲器) |
| 中文描述： | 3伏高級堆疊芯片級封裝存儲器（3V的閃速存儲器和靜態(tài)存儲器） |
| 文件頁數(shù)： | 40/64頁 |
| 文件大小： | 927K |
| 代理商： | 28F1604C3 |
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28F1602C3, 28F1604C3, 28F3204C3
34
Preliminary
6.2.1
F-RP# Connected to System Reset
The use of F-RP# during system reset is important with automated program/erase devices since the
system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. Intel recommends connecting F-RP# to
the system CPU RESET# signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when F-V
CC
voltages are above V
LKO
. Since
both F-WE# and F-CE# must be low for a command write, driving either signal to V
IH
will
inhibit
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until F-RP# is brought to V
IH
, regardless of the state of its control
inputs.
By holding the device in reset (F-RP# connected to system PowerGood) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
6.2.2
F-V
CC
, F-V
PP
and F-RP# Transition
The CUI latches commands as issued by
system software and is not altered by F-V
PP
or F-CE#
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after
F-V
CC
transitions above V
LKO
(Lockout voltage), is read array mode.
After any program or block erase operation is complete (even after F-V
PP
transitions down to
V
PPLK
), the CUI must be reset to read array mode via the Read Array command if access to the
flash memory array is desired.
NOTE:
1. A resistor can be used if the F-V
CC
supply can sink adequate current based on resistor value.
Figure 12. Example Power Supply Configurations
V
CC
V
PP
12 V Fast Programming
Absolute Write Protection With V
PP
≤
V
PPLK
System Supply
12 V Supply
10
≤
K
V
CC
V
PP
System Supply
12 V Supply
Low Voltage and 12 V Fast Programming
V
CC
V
PP
System Supply
Prot#
(Logic Signal)
V
CC
V
PP
System Supply
Low-Voltage Programming
Low-Voltage Programming
Absolute Write Protection via Logic Signal
(Note 1)
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