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參數(shù)資料
| 型號： | 29F4000 |
| 廠商： | Macronix International Co., Ltd. |
| 英文描述： | 4M-BIT [512Kx8/256Kx16] CMOS FLASH MEMORY |
| 中文描述： | 4分位[512Kx8/256Kx16]的CMOS閃存 |
| 文件頁數(shù)： | 10/44頁 |
| 文件大?。?/td> | 710K |
| 代理商： | 29F4000 |
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10
P/N:PM0439
MX29F400T/B
REV. 1.6, NOV. 12, 2001
ERASE SUSPEND
This command only has meaning while the state ma-
chine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Sector Erase operation. When the Erase Suspend com-
mand is written during a sector erase operation, the de-
vice requires a maximum of 100us to suspend the erase
operations. However, When the Erase Suspend command
is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends
the erase operation. After this command has been ex-
ecuted, the command register will initiate erase suspend
mode. The state machine will return to read mode auto-
matically after suspend is ready. At this time, state ma-
chine only allows the command register to respond to
the Read Memory Array, Erase Resume and program
commands.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend pro-
gram operation is complete, the system can once again
read array data within non-suspended sectors.
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.Another Erase Suspend command can
be written after the chip has resumed erasing.
SET-UP AUTOMATIC PROGRAM
COMMANDS
To initiate Automatic Program mode, A three-cycle com-
mand sequence is required. There are two "unlock" write
cycles. These are followed by writing the Automatic Pro-
gram command A0H.
Once the Automatic Program command is initiated, the
next WEor CE, pulse causes a transition to an active
programming operation. Addresses are latched on the
falling edge, and data are internally latched on the
rising edge of the WE or CE, whichever happens first,
pulse. The rising edge of WE or CE, whichever happens
first, also begins the programming operation. The sys-
tem is not required to provide further controls or timings.
The device will automatically provide an adequate inter-
nally generated program pulse and verify margin.
If the program opetation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the program operation
exceed internal timing limit. The automatic programming
operation is completed when the data read on Q6 stops
toggling for two consecutive read cycles and the data
on Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read mode(no
program verify command is required).
DATA POLLING-Q7
The MX29F400T/B also features Data Polling as a
method to indicate to the host system that the Auto-
matic Program or Erase algorithms are either in progress
or completed.
While the Automatic Programming algorithm is in opera-
tion, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an at-
tempt to read the device will produce the true data last
written to Q7. The Data Polling feature is valid after the
rising edge of the fourth WEor CE, whichever happens
first, pulse of the four write pulse sequences for auto-
matic program.
While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data Polling feature is valid after the rising
edge of the sixth WE or CE, whichever happens first
pulse of six write pulse sequences for automatic chip/
sector erase.
The Data Polling feature is active during Automatic Pro-
gram/Erase algorithm or sector erase time-out.(see sec-
tion Q3 Sector Erase Timer)
RY/BY:Ready/Busy
The RY/BY is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algorithm
is in progress or complete. The RY/BY status is valid
after the rising edge of the final WE or CE, whichever
happens first, pulse in the command sequence. Since
RY/BY is an open-drain output, several RY/BY pins can
be tied together in parallel with a pull-up resistor to Vcc.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 29F400B-12PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4MEGABIT (512K x 8/ 256K x 16) 5VOLT SECTOR ERASE CMOS FLASH MEMORY |
| 29F400B-12PI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4MEGABIT (512K x 8/ 256K x 16) 5VOLT SECTOR ERASE CMOS FLASH MEMORY |
| 29F400B-12TC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4MEGABIT (512K x 8/ 256K x 16) 5VOLT SECTOR ERASE CMOS FLASH MEMORY |
| 29F400B-12TI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4MEGABIT (512K x 8/ 256K x 16) 5VOLT SECTOR ERASE CMOS FLASH MEMORY |
| 29F400B-90PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4MEGABIT (512K x 8/ 256K x 16) 5VOLT SECTOR ERASE CMOS FLASH MEMORY |
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