參數(shù)資料
型號(hào)： 29PL256N
廠商： Spansion Inc.
英文描述： 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
中文描述： 256/128/128字節(jié)（16/8/8 M中的x 16位），3.0伏的CMOS只同步讀/寫，頁(yè)模式閃存
文件頁(yè)數(shù)： 35/74頁(yè)
文件大?。?/td> 1968K
代理商： 29PL256N
June 6, 2007 S29PL-N_00_A5
S29PL-N MirrorBit
Flash Family
35
D a t a
S h e e t
( P r e l i m i n a r y )
7.4.7
Accelerated Program
Accelerated single word programming, write buffer programming, sector erase, and chip erase operations are
enabled through the ACC function. This method is faster than the standard chip program and erase command
sequences.
The accelerated chip program and erase functions must not be used more than 10 times per sector.
In addition, accelerated chip program and erase should be performed at room temperature (25
°
C
±
10
°
C).
This function is primarily intended to allow faster manufacturing throughput at the factory. If the system
asserts V
HH
on this input, the device automatically enters the aforementioned Unlock Bypass mode and uses
the higher voltage on the input to reduce the time required for program and erase operations. The system can
then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note that if a
Write-to-Buffer-Abort Reset
is required while in Unlock Bypass mode, the full 3-cycle RESET command
sequence must be used to reset the device. Removing V
HH
from the ACC input, upon completion of the
embedded program or erase operation, returns the device to normal operation.
Sectors must be unlocked prior to raising WP#/ACC to V
HH
.
The WP#/ACC must not be at V
HH
for operations other than accelerated programming and accelerated
chip erase, or device damage can result.
Set the ACC pin at V
CC
when accelerated programming not in use.
7.4.8
Unlock Bypass
The device features an Unlock Bypass mode to facilitate faster word programming. Once the device enters
the Unlock Bypass mode, only two write cycles are required to program data, instead of the normal four
cycles.
This mode dispenses with the initial two unlock cycles required in the standard program command sequence,
resulting in faster total programming time.
Table 12.1,
Memory Array Commands
on page 66
shows the
requirements for the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass Reset
commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass
reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle
need only contain the data 00h. The bank then returns to the read mode.
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