參數(shù)資料
型號(hào)： 29PL256N
廠商： Spansion Inc.
英文描述： 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
中文描述： 256/128/128字節(jié)（16/8/8 M中的x 16位），3.0伏的CMOS只同步讀/寫(xiě)，頁(yè)模式閃存
文件頁(yè)數(shù)： 47/74頁(yè)
文件大?。?/td> 1968K
代理商： 29PL256N
June 6, 2007 S29PL-N_00_A5
S29PL-N MirrorBit
Flash Family
47
D a t a
S h e e t
( P r e l i m i n a r y )
8.4
Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed to
0
), this
bit locks all PPB and when cleared (programmed to
1
), unlocks each sector. There is only one PPB Lock Bit
per device.
Notes
1. No software command sequence unlocks this bit unless the device is in the password protection
mode; only a hardware reset or a power-up clears this bit.
2. The PPB Lock Bit must be set (programmed to
0
) only after all PPBs are configured to the desired
settings.
8.5
Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent Sector Protection
Mode by requiring a 64-bit password for unlocking the device PPB Lock Bit. In addition to this password
requirement, after power up and reset, the PPB Lock Bit is set
0
to maintain the password mode of operation.
Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock
Bit, allowing for sector PPBs modifications.
Notes
1. There is no special addressing order required for programming the password. Once the Password
is written and verified, the Password Mode Locking Bit must be set to prevent access.
2. The Password Program Command is only capable of programming
0
s. Programming a
1
after a
cell is programmed as a
0
results in a time-out with the cell as a
0
.
3. The password is all
1
s when shipped from the factory.
4. All 64-bit password combinations are valid as a password.
5. There is no means to verify what the password is after it is set.
6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and
further password programming.
7. The Password Mode Lock Bit is not erasable.
8. The lower two address bits (A1 – A0) are valid during the Password Read, Password Program, and
Password Unlock.
9. The exact password must be entered in order for the unlocking function to occur.
10.The Password Unlock command cannot be issued any faster than 1 μs at a time to prevent a
hacker from running through all the 64-bit combinations in an attempt to correctly match a
password.
11.Approximately 1 μs is required for unlocking the device after the valid 64-bit password is given to
the device.
12.Password verification is only allowed during the password programming operation.
13.All further commands to the password region are disabled and all operations are ignored.
14.If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB
Lock Bit.
15.Entry command sequence must be issued prior to any of any operation and it disables reads and
writes for Bank A. Reads and writes for other banks excluding Bank A are allowed.
16.If the user attempts to program or erase a protected sector, the device ignores the command and
returns to read mode.
17.A program or erase command to a protected sector enables status polling and returns to read
mode without having modified the contents of the protected sector.
18.The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing
individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device.
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