參數(shù)資料
型號(hào)： 29PL256N
廠商： Spansion Inc.
英文描述： 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
中文描述： 256/128/128字節(jié)（16/8/8 M中的x 16位），3.0伏的CMOS只同步讀/寫(xiě)，頁(yè)模式閃存
文件頁(yè)數(shù)： 42/74頁(yè)
文件大小： 1968K
代理商： 29PL256N
42
S29PL-N MirrorBit
Flash Family
S29PL-N_00_A5 June 6, 2007
D a t a
S h e e t
( P r e l i m i n a r y )
Figure 7.6
Simultaneous Operation Block Diagram for S29PL129N
7.6
Writing Commands/Command Sequences
During a write operation, the system must drive CE# and WE# to V
IL
and OE# to V
IH
when providing an
address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is
latched on the 1st rising edge of WE# or CE#. An erase operation can erase one sector, multiple sectors, or
the entire device.
Table 6.1 on page 18
and
Table 6.2 on page 19
indicate the address space that each
sector occupies. The device address space is divided into four banks: Banks B and C contain only 128 Kword
sectors, while Banks A and D contain both 32 Kword boot sectors in addition to 128 Kword sectors. A
bank
address
is the set of address bits required to uniquely select a bank. Similarly, a
sector address
is the
address bits required to uniquely select a sector. I
CC2
in
DC Characteristics
on page 57
represents the active
current specification for the write mode. See
AC Characteristics
on page 59
contains timing specification
tables and timing diagrams for write operations.
7.7
Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#
is driven low for at least a period of t
RP
, the device immediately terminates any operation in progress, tristates
all outputs, and ignores all read/write commands for the duration of the RESET# pulse. The device also
resets the internal state machine to reading array data.
To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to
accept another command sequence.
When RESET# is held at V
SS
, the device draws CMOS standby current (I
CC4
). If RESET# is held at V
IL
, but
not at V
SS
, the standby current is greater.
RESET# may be tied to the system reset circuitry which enables the system to read the boot-up firmware
from the Flash memory upon a system reset.
See
Figure 11.5 on page 56
and
Figure 11.8 on page 60
for timing diagrams.
V
CC
V
SS
B
a
nk 1A Addre
ss
B
a
nk 1B Addre
ss
A21 – A0
RE
S
ET#
WE#
CE1#
DQ0 – DQ15
CE2#
S
t
a
te
Control
a
nd
Comm
a
nd
Regi
s
ter
RY/BY#
B
a
nk 1A
X-Decoder
OE#
S
t
a
t
us
Control
A21 – A0
A21 – A0
A
A
D
DQ15 – DQ0
D
D
D
M
u
x
M
u
x
M
u
x
B
a
nk 1B
X-Decoder
Y
a
t
B
a
nk 2A
X-Decoder
B
a
nk 2B
X-Decoder
Y
a
t
B
a
nk 2A Addre
ss
B
a
nk 2B Addre
ss
CE1# = L
CE2# = H
CE1# = H
CE2# = L
WP#/ACC
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