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參數(shù)資料
| 型號(hào)： | 29PL256N |
| 廠商： | Spansion Inc. |
| 英文描述： | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| 中文描述： | 256/128/128字節(jié)（16/8/8 M中的x 16位），3.0伏的CMOS只同步讀/寫，頁模式閃存 |
| 文件頁數(shù)： | 50/74頁 |
| 文件大?。?/td> | 1968K |
| 代理商： | 29PL256N |
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50
S29PL-N MirrorBit
Flash Family
S29PL-N_00_A5 June 6, 2007
D a t a
S h e e t
( P r e l i m i n a r y )
9.
Power Conservation Modes
9.1
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET#
inputs are both held at V
CC
±0.2 V. The device requires standard access time (t
CE
) for read access, before it
is ready to read data. If the device is deselected during erasure or programming, the device draws active
current until the operation is completed. I
CC3
in
DC Characteristics
on page 57
represents the standby current
specification
9.2
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous mode. the
device automatically enables this mode when addresses remain stable for t
ACC
+ 20 ns. The automatic sleep
mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is latched and always available to
the system. I
CC6
in
DC Characteristics
on page 57
represents the automatic sleep mode current specification.
9.3
Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#
is driven low for at least a period of t
RP
, the device immediately terminates any operation in progress, tristates
all outputs, resets the configuration register, and ignores all read/write commands for the duration of the
RESET# pulse. The device also resets the internal state machine to reading array data. The operation that
was interrupted should be reinitiated once the device is ready to accept another command sequence to
ensure data integrity.
When RESET# is held at V
SS
±0.2 V, the device draws CMOS standby current (I
CC4
). If RESET# is held at
V
IL
but not within V
SS
±0.2 V, the standby current is greater.
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
9.4
Output Disable (OE#)
When the OE# input is at V
IH
, output from the device is disabled. The outputs are placed in the high
impedance state.
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