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| 型號： | 29PL256N |
| 廠商： | Spansion Inc. |
| 英文描述： | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| 中文描述： | 256/128/128字節(jié)（16/8/8 M中的x 16位），3.0伏的CMOS只同步讀/寫，頁模式閃存 |
| 文件頁數(shù)： | 65/74頁 |
| 文件大小： | 1968K |
| 代理商： | 29PL256N |
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June 6, 2007 S29PL-N_00_A5
S29PL-N MirrorBit
Flash Family
65
D a t a
S h e e t
( P r e l i m i n a r y )
11.8.5
Erase and Programming Performance
Notes
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V
CC
, 10,000 cycles. Additionally, programming typicals
assume checkerboard pattern. All values are subject to change.
2. Under worst case conditions of 90°C, V
CC
= 2.7 V, 100,000 cycles. All values are subject to change.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster
than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 12.1
on page 66
and
Table 12.2 on page 68
for further information on command definitions.
6. Contact the local sales office for minimum cycling endurance values in specific applications and operating conditions.
7. See Application Note
Erase Suspend/Resume Timing
for more details.
8. Word programming specification is based upon a single word programming operation not utilizing the write buffer.
11.8.6
BGA Ball Capacitance
Notes
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
Parameter
(Notes)
Device
Condition
Typ
(Note 1)
Max
(Note 2)
Unit
Comments
(Notes)
Sector Erase Time
128 Kword
V
CC
1.6
7
s
Excludes 00h programming
prior to erasure (
4
)
ACC
1.6
7
32 Kword
V
CC
0.3
4
ACC
0.3
4
Chip Erase Time
V
CC
202 (PL256N)
100 (PL127N)
100(PL129N)
900 (PL256N)
450 (PL127N)
450 (PL129N)
s
ACC
130 (PL256N)
65 (PL127N)
65 (PL129N)
512 (PL256N)
256 (PL127N)
256 (PL129N)
Word Programming Time
V
CC
40
400
μs
Excludes system level overhead (
5
)
ACC
24
240
Effective Word Programming Time
utilizing Program Write Buffer
V
CC
9.4
94
μs
ACC
6
60
Total 32-Word Buffer
Programming Time
V
CC
300
3000
μs
ACC
192
1920
Chip Programming Time
using 32-Word Buffer (
3
)
V
CC
157.3 (PL256N)
78.6 (PL127N)
78.6 (PL129N)
315 (PL256N)
158 (PL127N)
158 (PL129N)
s
Excludes system level overhead (
5
)
ACC
100 (PL256N)
50 (PL127N)
50 (PL129N)
200 (PL256N)
100 (PL127N)
100 (PL129N)
Erase Suspend/Erase Resume
<20
μs
Program Suspend/Program Resume
<20
μs
Parameter
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
7
10
pF
C
OUT
Output Capacitance
V
OUT
= 0
8
12
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
8
11
pF
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