參數(shù)資料
型號(hào)： 73M2921-IG
廠商： Electronic Theatre Controls, Inc.
英文描述： Advanced Single Chip Modem
中文描述： 先進(jìn)的單芯片調(diào)制解調(diào)器
文件頁(yè)數(shù)： 17/41頁(yè)
文件大?。?/td> 222K
代理商： 73M2921-IG
73M2921
Advanced Single
Chip Modem
February 99 Rev M
TDK Semiconductor
Page 17 of 41
UNSOLICITED RESPONSE
A
8,17
(low) interrupt can be the result of the
μ
C doing a General register access (GRA, previously described), or an
Unsolicited Response indicating there has been a change in one of the status registers. An Unsolicited Response is
defined as any response or information sent from the 73M2921 to the mailbox, which was the result of an unsolicited
interrupt from the internal DSP. The general register set
8,17
interrupt service routine must always check bit 7 of the
Control byte to determine whether the interrupt was the result of a GRA in progress or an Unsolicited Response from the
General register set status registers. An Unsolicited Response must always be serviced first, then the GRA in progress
can be resumed. The data received from the 73M2921 is broken into Control and Data fields. Address 10b is the Control
byte and Address 11b is the Data byte.
As an example, the user can enable each individual bit in each Detect Register to create an interrupt every time a
detect bit has changed state. Once a detect bit is enabled, any change in state for that bit will trigger an Unsolicited
Interrupt which sets bit 7 of the control byte to a one and the address bits of the Control byte to the address of the
register which contains the bit that changed state. The Data byte will contain the contents of that register. Reading the
mailbox clears the interrupt from the 73M2921 and allows further interrupts to occur.
The Control byte is broken down into bit segments as follows:
BIT 7
UR
BIT 6
WT/
%7
BIT 5
R/
:
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
---------- General Register Address --------------
UR = Unsolicited Response. Set if data is not response to last command.
WT/
%7
= Word Transfer/Byte Transfer. Will always be zero (byte transfer) during Unsolicited Interrupt.
R/
:
= Read/Write. Shadows last command. (Don’t care).
The General Register Address holds detect register address which triggered the interrupt.
In the example shown in Figure 6, the UR bit 7 will be set informing the microcontroller that this is an unsolicited
response. The WT/
%7
bit is clear as this is a byte transfer. The address bits hold the address of Detect Register
1 (09h), which generated the interrupt. The Data byte contains the Detect register information. In this case an S1
signal is being received.
FIGURE 6 – Unsolicited Interrupt Example
1
X
X
X = Don't Care
0
1
0
0
1
0
1
0
0
0
0
0
0
MS Byte
LS Byte
UD[0-7]
MSB
LSB
UNSOLICITED RESPONSE READ OPERATION
DETECT REGISTER 1 INFORMATION
CONTROL BYTE
UA
XX
10
11
XX
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