參數資料
型號: 73M2921-IG
廠商: Electronic Theatre Controls, Inc.
英文描述: Advanced Single Chip Modem
中文描述: 先進的單芯片調制解調器
文件頁數: 9/41頁
文件大?。?/td> 222K
代理商: 73M2921-IG
73M2921
Advanced Single
Chip Modem
February 99 Rev M
TDK Semiconductor
Page 9 of 41
REGISTER NAME:
D15
D14
CR0
ADDRESS: UA00, 01h (WRITE ONLY)
D9
D8
D7
D13
D12
D11
D10
D6
MAINCK (2:0)
D5
D4
D3
D2
D1
D0
DSPCK (2:0)
EN
DSPCK
MCLK (2:0)
EN
MCLK
EN
OSC
RESET
PSDIS
(1:0)
567'63
BIT NO.
D0
NAME
CONDITION
1
DESCRIPTION
Set to a logic 1 by the RESET pin, the RESET CHIP bit, or
by powering up the chip. To enable the DSP, the
567'63
bit must be high.
Causes a RESET interrupt to be continuously held for the
DSP. While low, the DSP will remain at instruction location
0x0000.
Used to mask the external power up source pins,
'7,
and
5,1*
.
A logical 1 on PSDIS[1] masks
'7,
. A logical 1 on
PSDIS[0] masks
5,1*
.
Resets the state of the 73M2921 putting it into a known
state. The function of this bit is similar to that of the RESET
pin, except that this bit does NOT change the setting of the
POWERUP SOURCE DISABLE bits. See Table 2.
Must be set to provide 4.608MHz to the timer. Default
values
shown
should
18.432 MHz oscillator frequency.
567'63
0
D1, D2
Power Up
Source
Disable[1,0]
D3
Reset Chip
D4,
D5,
D6
D7
Main Timer
Clock Divisor
D6
0
D5
1
D4
1
be
used
with
the
Enable
Oscillator
1
0
Enables the master oscillator. (Must be set to run)
Disables the oscillator and stops all chip activity.
For a clean MICCLK transition when stopping the clock (EN
MCLK=0), the EN MCLK bit must be turned off prior to the
oscillator (EN OSC) being disabled.
MICCLK enabled.
MICCLK disabled (Set to 0 if not using MICCLK).
Controls the frequency of the MICCLK output as a function
of the oscillator frequency. Default values shown should be
used with the 18.432 oscillator frequency. Set these to 0 if
not using MICCLK (See Table 3).
Set by the RESET pin, the RESET CHIP bit, or by powering
up the chip.
DSP clock enabled. (Must be set to run)
DSP clock disabled.
D8
Enable Micro-
processor
Clock
1
0
D9,
D10,
D11
Microcontroller
Clock Divisor
D11 D10
1
D9
1
1
D12
Enable DSP
Clock
1
0
D13,
D14,
D15
DSP Clock
D15 D14 D13
1
1
1
Controls the internal DSP clock frequency as a function of the
oscillator frequency. Default values shown should be used with
the 18.432 MHz oscillator frequency.
For a clean DSPCK transition when stopping the DSP (
567'63
=0), the
567'63
bit must be set low prior to the
oscillator (ENOSC) being disabled.
For a clean DSPCK transition when starting the DSP (
567'63
=1), the
567'63
bit must be set high after the
oscillator (ENOSC) is enabled. This happens automatically after reset or power up.
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