參數(shù)資料
型號: 73M2921-IG
廠商: Electronic Theatre Controls, Inc.
英文描述: Advanced Single Chip Modem
中文描述: 先進的單芯片調制解調器
文件頁數(shù): 24/41頁
文件大?。?/td> 222K
代理商: 73M2921-IG
73M2921
Advanced Single
Chip Modem
Page 24 of 41
TDK Semiconductor
February 99 Rev M
DETECT 1 ENABLE REGISTER
ADDRESS: 08h (08d, 01000b) MODE: SEE DET REG 1
BIT D7
CAS
BIT D6
S1
BIT D5
RES
BIT D4
EGY
BIT D3
HIP
BIT D2
CAR
BIT D1
RDLBD
BIT D0
RES
This is the enable register for Detect 1. Setting bits TO 1 in this register enables the unsolicited interrupt feature.
These bits have a 1 to 1 correspondence with Detect Register 1. The default value is “0”. See Detect Register 1.
DETECT REGISTER 1 (READ ONLY)
ADDRESS: 09h (09d, 01001b) MODE: SEE BELOW
BIT D7
CAS
BIT D6
S1
BIT D5
RES
BIT D4
EGY
BIT D3
HIP
BIT D2
CAR
BIT D1
RDLBD
BIT D0
RES
BIT NO.
D0
D1
D2
NAME
Reserved
RDLBD
Carrier Detect
CONDITION
DESCRIPTION
Reserved.
RDLB Detect
This bit will be set when conditions for V.24 circuit 104
are met by the modulation mode being used (Modem in
data mode).
This bit will be set if a handshake is currently in progress.
This bit is cleared by the 73M2921 when either a
handshake has been successful and the 73M2921 has
entered DATA mode, or when a handshake has been
aborted and the 73M2921 is placed into IDLE mode.
This bit will be set if receive level is above a
predetermined threshold.
Reserved.
This bit will be set if S1 (Unscrambled 1100 @ 1200b/s)
is detected. This bit is also used to detect a Retrain
request if connected V.22bis or V.22 and S1 is detected.
This bit will be set if the CAS tone (2130Hz + 2750 Hz) is
detected.
Valid in Data Mode
Valid in Data Mode
D3
Handshake in
progress
Valid in Data Mode
D4
Energy Detect
Valid in call Progress
Mode
D5
D6
Reserved
S1 Detect
Valid in Data Mode
D7
CAS Tone
Detect
Valid in All Modes
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