參數(shù)資料
型號(hào): 73M2921-IG
廠商: Electronic Theatre Controls, Inc.
英文描述: Advanced Single Chip Modem
中文描述: 先進(jìn)的單芯片調(diào)制解調(diào)器
文件頁數(shù): 4/41頁
文件大?。?/td> 222K
代理商: 73M2921-IG
73M2921
Advanced Single
Chip Modem
Page 4 of 41
TDK Semiconductor
February 99 Rev M
PIN DESCRIPTION
(continued)
POWER CONTROL
NAME
'7,
PIN
26
TYPE
I
DESCRIPTION
DATA TERMINAL INTERRUPT 0: Active Low Input with hysteresis.
Power up signal. The action of this pin can be masked by the PSDIS[1]
register bit. This pin would connect to EIA-232 connection DTR in many
applications. Requires a 50K
external pull up.
RING DETECT: Active Low Input with hysteresis. Power up signal. The
action of this pin can be masked by the PSDIS[0] register bit. This pin
would connect to the ring detect circuitry or the control microcontroller in
many applications. Requires a 50K
external pull up.
WAKE: Active Low Output. Indicates that a power up pin (
5,1*
or
'7,
) has been activated when the 73M2921 is in slave mode. The
latched signal remains true until a reset of the wake function by a write to
CR0 LSByte, or a chip reset. Requires a 50K
external pull up.
5,1*
24
I
:$.(
39
O
MICROCONTROLLER INTERFACE
NAME
&6
PIN
15
TYPE
I
DESCRIPTION
CHIP SELECT: Active Low Input. Enables data transfers on the
μ
P
parallel interface. Requires a 50K
external pull up.
READ: Active Low Input. Read enable signals for the mailbox/control
register interface.
WRITE: Active Low Input. Write enable signals for the mailbox/control
register interface.
ADDRESS: Address bits that are used by the
μ
P to communicate with
the 73M2921 mailbox and CR0.
DATA: Parallel data bus for the mailbox/CR0 interface.
INTERRUPT:
μ
C interrupt Active Low Output. Used as an interrupt to
the microcontroller indicating that the 73M2921 needs data or has a
request for the
μ
C. It is activated when the 73M2921 writes to the
mailbox and cleared when the μC reads the mailbox LSByte. Requires a
50K
external pull up.
5'
17
I
:5
16
I
UA[0:1]
13-14
I
UD [0:7]
8,17
5-12
18
I/O
O
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