參數(shù)資料
型號(hào): 73M2921-IG
廠商: Electronic Theatre Controls, Inc.
英文描述: Advanced Single Chip Modem
中文描述: 先進(jìn)的單芯片調(diào)制解調(diào)器
文件頁(yè)數(shù): 7/41頁(yè)
文件大小: 222K
代理商: 73M2921-IG
73M2921
Advanced Single
Chip Modem
February 99 Rev M
TDK Semiconductor
Page 7 of 41
POWER CONTROL TIMING
DESCRIPTION
Powerup input to active state
Powerup input to inactive state
MIN
250
50
TYP
MAX
UNIT
μs
μs
Table 5 - Power Control Timing
DCE-DTE INTERFACE
The 73M2921 is designed to interface with a synchronous port such as that found on the TDK 73M2910. It also
provides a parallel control interface. This parallel interface appears as an 8 bit memory mapped peripheral to the
host controller.
SERIAL DATA INTERFACE
The serial data interface is a four pin bi-directional port. It consists of the TXD and RXD data paths (LSBit
shifted in and out first, respectively), the TXCLK and RXCLK serial clock outputs associated with the data pins.
SYMBOL
TXDS
TXDH
TRD
DESCRIPTION
DATA to TXCLK
TXCLK to Data Hold
RXCLK to RXD Delay
MIN
TYP
Tbd
Tbd
Tbd
MAX
UNIT
ns
ns
ns
Table 3 - Serial Data Interface Timing
Synchronous Mode
FIGURE 7 - Serial Data Interface Timing Diagram
MICROCONTROLLER TO 73M2921 PARALLEL INTERFACE
The interface between the microcontroller (
μ
C) and the 73M2921 is accomplished through the 2 bit address
UA[1:0] and 8 bit data bus UD[7:0],
5'
,
:5
, and
&6
. The 73M2921 chip provides an interrupt output to the
μ
C
(
8,17
). The 73M2921 and the
μ
C communicate through two 16 bit registers, CR0 and the Mailbox; all
μ
C
accesses are 8 bit transfers. All reading and writing functions to and from the 73M2921 internal registers as well
TXD, RXD
TXCLK or
RXCLK
t
XDS
t
XDS
t
XDH
t
RD
Sample Time
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