IDT EJTAG System
Off-Chip and Probe Interfaces
79RC32438 User Reference Manual
20 - 80
November 4, 2002
Notes
The I
Zstate
specifies the current that a tri-stated (undriven) output driver and pull-up/down can provide. It
sets a limit for the drivers in the probe for JTAG_TCK, EJTAG_TMS, JTAG_TDI, JTAG_TRST_N, and
RSTN, and it sets a limit for the output driver on-chip for JTAG_TDO. This limit allows design of pull-up/
down resistors that can keep a logical level when no driver is controlling the signal.
C
Target
and C
Probe
are the capacitances in the target system for inputs and the capacitances for the
probe for outputs. Additional capacitance in the target system must be added to C
Probe
when designing the
output driver, and additional capacitance for the probe driver is added to C
Target
.
Mechanical Connector
Figure 20.42 shows the recommended EJTAG connector on a target system. The connector is a
common pin strip with dimensions 0.100” x 0.100”, for example, SAMTEC part number TSW-107-23-L-D or
compatible. The socket on the probe side must allow for an angled connector on the target system.
Symbol
Description
Condition
Min.
Type
Max.
Unit
Vcc I/O
Vcc I/O voltage
When stable
1.5
5.0
V
T
VIOactive
T
VIO
active indication
0.5
V
I
VIO
I
VIO
output current
20
mA
V
IL
Low-level input voltage
2.8V < T
VIO
-0.3
0.8
V
T
VIO
< 2.8V
-0.3
0.3*T
VIO
V
V
IH
High-level input voltage
2.8V < T
VIO
2.0
T
VIO
+0.3
V
T
VIO
< 2.8V
0.7*T
VIO
T
VIO
+0.3
V
V
OL
Low-level output voltage
2.8V < T
VIO
-0.3
.04
V
T
VIO
< 2.8V
-0.3
0.15*T
VIO
V
V
OH
High-level output voltage
2.8V < T
VIO
2.4
T
VIO
+0.3
V
T
VIO
< 2.8V
0.85*T
VIO
T
VIO
+0.3
V
I
IL
Low-level input current,
except RSTN
-8.0
mA
I
RST
RSTN low-level input
current
-10
mA
I
IH
High level input current
8.0
mA
I
OL
Low level output current
8.0
mA
I
OH
High level output current
-8.0
mA
I
Zstate
Tri-state input or output
current
0 < V
Sig
< T
VIO
-50
50
μA
C
Target
Capacitance for target
system
25
pF
C
Probe
Capacitance for probe
25
pF
Table 20.59 DC Electrical Characteristics