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參數(shù)資料
| 型號(hào)： | 91C94 |
| 廠商： | SMSC Corporation |
| 英文描述： | ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM |
| 中文描述： | 的ISA / PCMCIA的單芯片以太網(wǎng)控制器與RAM |
| 文件頁(yè)數(shù)： | 100/120頁(yè) |
| 文件大小： | 447K |
| 代理商： | 91C94 |
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80
The cycle time is defined as the time between
leading edges of read from the Data Register, or
equivalently between trailing edges of write to
the Data Register.
For example, in an ISA
system the cycle time of a 16 bit transfer will be
at least 2 clocks for the I/O access to the
LAN91C94 + one clock for the memory cycle) =
3 clocks. In absolute time it means 375ns for a
8MHz bus, and 240ns for a 12.5 MHz bus.
The cycle time will not increase when configured
for full duplex mode, because the CSMA/CD
memory arbitration requests are sequenced by
the DMA logic and never overlap.
DMA BLOCK
The DMA block resides between the CSMA/CD
block and the arbiter. It can interface both the
data path and the control path of the CSMA/CD
block for different operations.
Its functions include the following:
Start
transmission
process
into
the
CSMA/CD block.
Generate CSMA/CD side addresses for
accessing memory during transmit and
receive operations.
Generate MMU memory requests and verify
success.
Compute byte count and write it in first
locations of receive packet.
Write transmit status word in first locations
of transmit packet.
Determine if enough memory is available
for reception.
De-allocate transmit memory after suitable
completion.
De-allocate receive memory upon error
conditions.
Initiate retransmissions upon collisions (if
less than 16 retries).
Terminate reception and release memory if
packet is too long.
The specific nature of each operation and its
trigger event are:
1)
TX operations will begin if TXENA is set
and TX FIFO is not empty. The DMA logic
does not need to use the TX PACKET
NUMBER, it goes directly from the FIFO to
the MMU. However the DMA logic controls
the removal of the PACKET NUMBER from
the FIFO.
2)
Generation of CSMA/CD side addresses
into memory: Independent 11 bit counters
are kept for transmit and receive in order to
allow full-duplex operation.
3)
MMU requests for allocation are generated
by the DMA logic upon reception.
The
initial allocation request is issued when the
CSMA block indicates an active reception. If
allocation succeeds, the DMA block stores
the packet number assigned to it, and
generates write arbitration requests for as
long as the CSMA/CD FIFO is not empty.
In parallel the CSMA/CD completes the
address filtering and notifies the DMA of an
address match. If there is no address
match, the DMA logic will release the
allocated memory and stop reception.
4)
When the CSMA/CD block notifies the DMA
logic that a receive packet was completed,
if the CRC is OK, the DMA will either write
the previously stored packet number into
the RX PACKET NUMBER FIFO (to be
processed by the CPU), or if the CRC is
bad the DMA will just issue a release
command to the MMU (and the CPU will
never see that packet).
Packets with bad CRC can be received if
the RCV_BAD bit in the configuration
register is set.
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