參數(shù)資料
型號: 91C94
廠商: SMSC Corporation
英文描述: ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM
中文描述: 的ISA / PCMCIA的單芯片以太網(wǎng)控制器與RAM
文件頁數(shù): 106/120頁
文件大小: 447K
代理商: 91C94
86
Reverse Polarity Function
In the 10BASE-T mode, the PHY monitors for
receiver polarity reversal due to crossed wires
and corrects by reversing the signal internally.
Collision Detection Function
In the 10BASE-T mode, a collision state is
indicated
when
there
are
simultaneous
transmissions and receptions on the twisted pair
link. During a collision state, the nCOLL signal
is asserted. If the received data ends and the
transmit control signal is still active, the transmit
data is sent to the MAC within 9 bit times. The
nCOLL signal is de-asserted within 9 bit times
after
the
collision
terminates.
In
the AUI mode, the external transceiver sends a
10MHz signal to the PHY upon detection of a
collision.
Link Integrity
The PHY test for a faulty twisted-pair link. In the
absence of transmit data, link test pulses are
transmitted every 16+/-18ms after the end of the
last transmission or link pulse on the twisted
pair medium. If neither valid data nor link test
pulses are received within 10 to 150ms, the link
is declared bad and both data transmission as
well as the operational loopback function are
disabled.
The Link Integrity function can be
disabled
for
pre-10BASE-T
twisted-pair
networks.
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