- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄294733 > 91C94 (SMSC Corporation) ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM PDF資料下載
參數(shù)資料
| 型號(hào)： | 91C94 |
| 廠商： | SMSC Corporation |
| 英文描述： | ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM |
| 中文描述： | 的ISA / PCMCIA的單芯片以太網(wǎng)控制器與RAM |
| 文件頁(yè)數(shù)： | 94/120頁(yè) |
| 文件大?。?/td> | 447K |
| 代理商： | 91C94 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)當(dāng)前第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)
75
AUTO
RELEASE
-
When
set,
successful
transmit packets are not written into completion
FIFO,
and
their
memory
is
released
automatically.
1)
One interrupt per packet: enable TX INT,
set AUTO RELEASE=0.
The software driver
can find the completion result in memory and
process the interrupt one packet at a time.
Depending on the completion code the driver
will take different actions. Note that the transmit
process
is
working
in
parallel
and
other
transmissions might be taking place.
The
LAN91C94
is
virtually
queuing
the
packet
numbers and their status words.
In this case, the transmit interrupt service
routine can find the next packet number to be
serviced by reading the TX DONE PACKET
NUMBER at the FIFO PORTS register.
This
eliminates the need for the driver to keep a list
of packet numbers being transmitted.
The
numbers are queued by the LAN91C94 and
provided back to the CPU as their transmission
completes.
2)
One interrupt per sequence of packets:
Enable TX EMPTY INT and TX INT, set AUTO
RELEASE=1. TX EMPTY INT is generated only
after transmitting the last packet in the FIFO.
TX INT will be set on a fatal transmit error
allowing the CPU to know that the transmit
process has stopped and therefore the FIFO will
not be emptied.
This mode has the advantage of a smaller CPU
overhead, and faster memory de-allocation.
Note that when AUTO RELEASE=1 the CPU is
not provided with the packet numbers that
completed successfully.
Note: The pointer register is shared by any
process accessing the LAN91C94 memory. In
order to allow processes to be interruptable,
the
interrupting
process
is
responsible
for
reading the pointer value before modifying it,
saving it, and restoring it before returning from
the interrupt.
Typically there would be three processes using
the pointer:
1)
Transmit
loading
(sometimes
interrupt
driven)
2)
Receive unloading (interrupt driven)
3)
Transmit Status reading (interrupt driven).
1) and 3) also share the usage of the Packet
Number
Register.
Therefore
saving
and
restoring the PNR is also required from interrupt
service routines.
POWER DOWN
The LAN91C94 can enter power down mode by
means of the PWRDWN pin (pin 68) or the
PWRDN bit (Control Register, bit 13).
The
power down current is 8 mA.
When in power
down mode, the LAN91C94 will:
- Stop the crystal oscillator
- Tristate:
Data Bus
Interrupts
nIOCS16
10BASE-T and AUI outputs
Turn off analog bias currents
- Drive the EEPROM and ROM outputs inactive
- Preserve contents of registers and memory
The PWRDWN pin is internally gated with the
RESET (RESET pin before de-glitching) and
with the SRESET bit (COR bit 7). This gating
function
internally
negates
power
down
whenever RESET is high or SRESET is high to
allow the oscillator to run during RESET. Except
for this gating function, all other uses of the
RESET pin use a de-glitched version of the
signal as defined in the pin description section.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 92_TNC-50-0-4/111_NE | BOARD TERMINATED, FEMALE, TNC CONNECTOR, SURFACE MOUNT, JACK |
| 92_TNC-50-0-4/111_NM | BOARD TERMINATED, FEMALE, TNC CONNECTOR, SURFACE MOUNT, JACK |
| 92082-314 | 14 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
| 92082-316 | 16 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
| 92082-318 | 18 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 91CCC3 | 制造商:Wirepro 功能描述:Connector Accessories Cap and Chain For Receptacle |
| 91-CCC3 | 制造商:CDM ELECTRONIC FORMERLY WPI 功能描述:connector accessory,circular microphone,cap and chain for receptacle |
| 91-CCC-3 | 制造商:Amphenol Corporation 功能描述: 制造商:TE Connectivity 功能描述: |
| 91CR10 | 制造商:TT Electronics / BI Technologies 功能描述:Res Cermet Trimmer 10 Ohm 20% 1/2W 1(Elec)/1(Mech)Turn (9.53 X 9.78 X 7.11mm) Pin Thru-Hole Box |
| 91CR100 | 功能描述:微調(diào)電阻 - 通孔 3/8inch 100 Thumbwheel RoHS:否 制造商:Vishay/Sfernice 產(chǎn)品:Trimmer Resistors - Multi Turn 產(chǎn)品類型:Multiturn 轉(zhuǎn)數(shù):14 錐度:Linear 電阻:10 kOhms 電壓額定值:250 V 端接類型:Pin 功率額定值:250 mW (1/4 W) 容差:10 % 溫度系數(shù):100 PPM / C |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。