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參數(shù)資料
| 型號(hào)： | 91C94 |
| 廠商： | SMSC Corporation |
| 英文描述： | ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM |
| 中文描述： | 的ISA / PCMCIA的單芯片以太網(wǎng)控制器與RAM |
| 文件頁數(shù)： | 73/120頁 |
| 文件大小： | 447K |
| 代理商： | 91C94 |
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56
I/O SPACE - BANK2
OFFSET
6
NAME
POINTER REGISTER
TYPE
READ/WRITE
SYMBOL
PTR
HIGH
BYTE
RCV
AUTO
INCR.
READ
ETEN
0
POINTER HIGH
0
LOW
BYTE
POINTER LOW
0
POINTER REGISTER:
The value of this
register determines the address to be accessed
within the transmit or receive areas. It will auto-
increment on accesses to the data register when
AUTO INCR. is set. The increment is by one for
every byte access, and by two for every word
access.
When RCV is set the address refers to the
receive area and uses the output of RX FIFO as
the packet number; when RCV is clear the
address refers to the transmit area and uses the
packet number at the Packet Number Register.
READ bit determines the type of access to
follow.
If the READ bit is high the operation
intended is a read. If the READ bit is low the
operation is a write.
Loading a new pointer
value, with the READ bit high, generates a pre-
fetch into the Data Register for read purposes.
Readback of the pointer will indicate the value of
the address last
accessed
by
the
CPU
(rather than the last pre-fetched).
This allows
any interrupt routine that uses the pointer to
save it and restore it without affecting the
process being interrupted.
The Pointer Register should not be loaded until
400ns after the last write operation to the Data
Register to ensure that the Data Register FIFO
is empty.
On reads, if IOCHRDY is not connected to the
host, the Data Register should not be read
before 400ns after the pointer was loaded to
allow the Data Register FIFO to fill.
If the pointer is loaded using 8 bit writes, the low
byte should be loaded first and the high byte
last.
ETEN bit
When set, enables Early Transmit
underrun detection.
Normal operation when
clear.
Note: If AUTO INCR. is not set, the pointer must
be loaded with an even value.
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