- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄294733 > 91C94 (SMSC Corporation) ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM PDF資料下載
參數(shù)資料
| 型號： | 91C94 |
| 廠商： | SMSC Corporation |
| 英文描述： | ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM |
| 中文描述： | 的ISA / PCMCIA的單芯片以太網(wǎng)控制器與RAM |
| 文件頁數(shù)： | 98/120頁 |
| 文件大?。?/td> | 447K |
| 代理商： | 91C94 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁當(dāng)前第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁
79
The arbiter uses the pointer register as the CPU
provided address, and the internal DMA address
from the CSMA/CD side as the addresses to be
provided to the MMU.
The data path routed by the arbiter goes
between memory (the data path does not go
through the MMU) on one side and either the
CPU side bus or the data path of the CSMA/CD
core.
The data path between memory and the Data
Register is in fact buffered by a small FIFO in
each direction.
The FIFOs beneath the Data
Register can be read and written as bytes or
words, in any sequential combination.
The
presence of these FIFOs makes sure that word
transfers are possible on the system bus even if
the address loaded into the pointer is odd.
BUS INTERFACE
The bus interface handles the data, address and
control interfaces as a superset of the ISA and
PCMCIA specifications and allows 8 or 16 bit
adapters to be designed with the LAN91C94
with no glue to interface the ISA or PCMCIA
bus.
The functions done in this block are address
decoding for I/O and ROM memory (including
address relocation support) for ISA, data path
routing, sequential memory address support,
optional
wait
state
generation,
boot
ROM
support,
EEPROM
setup
function,
bus
transceiver
control,
and
interrupt
generation/selection.
For ISA, I/O address decoding is done by
comparing A15-A4 to the I/O BASE address
determined in part by the upper byte of the
BASE
ADDRESS
REGISTER,
and
also
requiring that AEN be low. If the above address
comparison is satisfied and the LAN91C94 is in
16 bit mode, nIOCS16 will be asserted (low).
A valid comparison does not yet indicate a valid
I/O cycle is in progress, as the addresses could
be used for a memory cycle, or could even
glitch through a valid value. Only when nIORD
or nIOWR are activated the I/O cycle begins.
In PCMCIA mode, A4-A15 are ignored for I/O
decodes, which rely on the PCMCIA host,
decoding for the slot. Input A10 for ISA is used
as an output (nFWE) for PCMCIA to enable
Flash Memory Write for programming the
attribute memory. It is valid only when nWE is
0 and COR2 is 1. nA11/nFCS is used to select
the Flash Memory Chip.
WAIT STATE POLICY
The LAN91C94 can work on most system buses
without having to add wait states.
The two
parameters that determine the memory access
profile are the read access time and the cycle
time into the Data Register.
The read access time is 40ns and the cycle time
is 185ns. If any one of them does not satisfy
the application requirements, wait states should
be added.
If the access time is the problem, IOCHRDY
should be negated for all accesses to the
LAN91C94.
This
can
be
achieved
by
programming the NO WAIT ST bit in the
configuration register to 0. The LAN91C94 will
negate IOCHRDY for 100ns to 150ns on every
access to any register.
If the cycle time is the problem, programming
NO WAIT ST as described before will solve it
but
at
the
expense
of
slowing
down
all
accesses.
The
alternative
is
to
let
the
LAN91C94 negate IOCHRDY only when the
Data Register FIFOs require so. Namely, if NO
WAIT ST is set, IOCHRDY will only be negated
if a Data Register read cycle starts and there is
less than a full word in the read FIFO, or if a
write cycle starts and there is more than two
bytes in the write FIFO.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 92_TNC-50-0-4/111_NE | BOARD TERMINATED, FEMALE, TNC CONNECTOR, SURFACE MOUNT, JACK |
| 92_TNC-50-0-4/111_NM | BOARD TERMINATED, FEMALE, TNC CONNECTOR, SURFACE MOUNT, JACK |
| 92082-314 | 14 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
| 92082-316 | 16 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
| 92082-318 | 18 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 91CCC3 | 制造商:Wirepro 功能描述:Connector Accessories Cap and Chain For Receptacle |
| 91-CCC3 | 制造商:CDM ELECTRONIC FORMERLY WPI 功能描述:connector accessory,circular microphone,cap and chain for receptacle |
| 91-CCC-3 | 制造商:Amphenol Corporation 功能描述: 制造商:TE Connectivity 功能描述: |
| 91CR10 | 制造商:TT Electronics / BI Technologies 功能描述:Res Cermet Trimmer 10 Ohm 20% 1/2W 1(Elec)/1(Mech)Turn (9.53 X 9.78 X 7.11mm) Pin Thru-Hole Box |
| 91CR100 | 功能描述:微調(diào)電阻 - 通孔 3/8inch 100 Thumbwheel RoHS:否 制造商:Vishay/Sfernice 產(chǎn)品:Trimmer Resistors - Multi Turn 產(chǎn)品類型:Multiturn 轉(zhuǎn)數(shù):14 錐度:Linear 電阻:10 kOhms 電壓額定值:250 V 端接類型:Pin 功率額定值:250 mW (1/4 W) 容差:10 % 溫度系數(shù):100 PPM / C |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。