參數(shù)資料
型號： 91C94
廠商： SMSC Corporation
英文描述： ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM
中文描述： 的ISA / PCMCIA的單芯片以太網(wǎng)控制器與RAM
文件頁數(shù)： 53/120頁
文件大?。?/td> 447K
代理商： 91C94
38
I/O SPACE - BANK0
OFFSET
2
NAME
EPH STATUS REGISTER
TYPE
READ ONLY
SYMBOL
EPHSR
This register stores the status of the last transmitted frame. This register value, upon individual
transmit packet completion, is stored as the first word in the memory area allocated to the packet.
Packet interrupt processing should use the copy in memory as the register itself will be updated by
subsequent packet transmissions. The register can be used for real time values (like TXENA and
LINK OK). If TXENA is cleared the register holds the last packet completion status.
HIGH
BYTE
TXUNRN
LINK_OK
RX_OVRN
CTR_ROL
EXC_DEF
LOST
CAR
LATCOL
0
X
LOW
BYTE
TX DEFR
LTX BRD
SQET
16COL
LTX MULT
MULCOL
SNGLCOL
TX_SUC
0
TXUNRN - Transmit Underrun. Set if underrun
occurs, it also clears TXENA bit in TCR. Cleared
by setting TXENA high. This bit should never be
set under normal operation.
LINK_OK - State of the 10BASE-T Link Integrity
Test. A transition on the value of this bit
generates an interrupt when the LE ENABLE bit
in the Control Register is set.
RX_OVRN - Upon receive overrun, the receiver
temporarily asserts this bit. The receiver stays
enabled and subsequent frames will be received
normally if memory becomes available.
The
RX_OVRN INT bit in the Interrupt Status
Register will also be set and stay set until
cleared by the CPU. Note that receive overruns
could occur only if receive memory allocations
fail.
CTR_ROL - Counter Roll over. When set one or
more 4 bit counters have reached maximum
count (15). Cleared by reading the ECR register.
EXC_DEF - Excessive deferral. When set
last/current transmit was deferred for more than
1518 * 2 byte times. Cleared at the end of every
packet sent.
LOST_CARR - Lost carrier sense. When set
indicates that Carrier Sense was not present at
end of preamble. Valid only if MON_CSN is
enabled. This condition causes TXENA bit in
TCR to be reset. Cleared by setting TXENA bit
in TCR.
LATCOL - Late collision detected on last
transmit frame. If set a late collision was
detected (later than 64 byte times into the
相關(guān)PDF資料
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92_TNC-50-0-4/111_NE BOARD TERMINATED, FEMALE, TNC CONNECTOR, SURFACE MOUNT, JACK
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