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參數(shù)資料
| 型號(hào)： | 91C94 |
| 廠(chǎng)商： | SMSC Corporation |
| 英文描述： | ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM |
| 中文描述： | 的ISA / PCMCIA的單芯片以太網(wǎng)控制器與RAM |
| 文件頁(yè)數(shù)： | 67/120頁(yè) |
| 文件大?。?/td> | 447K |
| 代理商： | 91C94 |
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50
I/O SPACE - BANK1
OFFSET
C
NAME
CONTROL REGISTER
TYPE
READ/WRITE
SYMBOL
CTR
HIGH
BYTE
0
RCV_BAD
PWRDN
AUTO
RELEASE
1
0
X
0
X
1
LOW
BYTE
LE
ENABLE
CR
ENABLE
TE
ENABLE
EEPROM
SELECT
RELOAD
STORE
0
X
0
RCV_BAD - When set, bad CRC packets are
received. When clear bad CRC packets do not
generate
interrupts
and
their
memory
is
released.
PWRDN - Active high bit used to enter power
down mode. Cleared by a write to any register in
the LAN91C94 I/O space or by hardware reset.
AUTO RELEASE - When set, transmit pages
are released by transmit completion if the
transmission was successful (when TX_SUC is
set). In that case there is no status word
associated
with
its
packet
number,
and
successful packet numbers are not even written
into the TX COMPLETION FIFO.
A sequence of transmit packets will only
generate an interrupt when the sequence is
completely transmitted (TX EMPTY INT will be
set), or when a packet in the sequence
experiences a fatal error (TX INT will be set).
Upon a fatal error TXENA is cleared and the
transmission
sequence
stops.
The
packet
number that failed is the present in the FIFO
PORTS
register, and its pages are not
released,
allowing the CPU to restart the sequence after
corrective action is taken.
LE ENABLE - Link Error Enable. When set it
enables the LINK_OK bit transition as one of the
interrupts merged into the EPH INT bit. Defaults
low (disabled). Writing this bit also serves as the
acknowledge by clearing previous LINK interrupt
conditions.
CR ENABLE - Counter Roll over Enable. When
set it enables the CTR_ROL bit as one of the
interrupts merged into the EPH INT bit. Defaults
low (disabled).
TE ENABLE - Transmit Error Enable. When set
it enables Transmit Error as one of the
interrupts merged into the EPH INT bit. Defaults
low (disabled). Transmit Error is any condition
that clears TXENA with TX_SUC staying low as
described in the EPHSR register.
EEPROM SELECT - This bit allows the CPU to
specify which registers the EEPROM RELOAD
or STORE refers to. When high, the General
Purpose Register is the only register read or
written.
When
low,
RELOAD
reads
Configuration, Base and
Individual
Address,
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