參數(shù)資料
型號(hào)： ACE9050
廠商： Mitel Networks Corporation
英文描述： System Controller and Data Modem(為蜂窩式手機(jī)提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器)
中文描述： 系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器（為蜂窩式手機(jī)提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器）
文件頁(yè)數(shù)： 20/52頁(yè)
文件大?。?/td> 366K
代理商： ACE9050
ACE9050
20
Associated register
BANK_SEL:
Bank Select register (Write only)
Bit
[7:5]
4
3
2
1
0
-
CS
BA 17
BA 16
BA 15
BA 14
Not used
Chip Select:
1 = CSE2N
0 = CSEPN
Banked Address A17 (see Table 27)
Banked Address A16 (see Table 27)
Banked Address A15 (see Table 27)
Banked Address A14 (see Table 27)
Name
Description
The processor memory map is thus split into two distinct
areas: Non Banked address (Root) and Banked address:
Non Banked address area (Root)
A[17:14]: The address lines A[17:16] are set to 11. The
address ines A[15:14] are dentical to the corresponding processor
address lines. This means the original area of the processor
memory map is mapped to the top of the external memory
address space.
CSE2N s never active, regardless of the value of the Bank_Sel
register bit 4. All access will be with CSEPN.
Banked Address area: A[17:14]
These address lines are the same as Bank Sel register bits
[3:0]. The programmer can in theory select up to 16 pages. This
is discussed in more detail in System Memory Map section.
CSE2N: The BANK SEL bit 4 determines whether this Chip
select line is enabled or the CSEPN.
Table 28 summarises operation in the two areas.
Address
area
Fig. 14 Banked Addressing block diagram
Fig. 15 Memory Map and Banked Addressing
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
REGISTERS
RAM
BANKED
BOOT ROM
0000
1000
8000
C000
FE00
FFFF
CPU
ADDRESS
15:0
0XXXX
1XXXX
2XXXX
3XXXX
SYSTEM
ADDRESS
256K ROM
SYSTEM
MEMORY MAP
64K
PROCESSOR
MEMORY MAP
Banked Address System Memory Map
The processor and the system memory map become different
because of the memory banking. The system memory map is
spit into 16K pages and the original processor Memory map
re-targeted. Refer to Fig. 15.
BANK_SEL
REGISTER
ID[3:0]
ID4
MUX
A
B
MUX
B
A
CONTROL
1 = A, 0 = B
AD15
AD14
ID [4:0]
17
16
15
14
4
4
5
V
DD
EPROM
SELECT
BA[17:14]
CSEPN
CSE2N
4
A[17:14]
A[17:14]
The banking is configured to occupy a 16K byte area of the
processor memory address space. It will thus create 16K byte
pages. This is configured in hardware and cannot be altered. It
is achieved by decoding the upper 2 bits of the processor
Address bus. If the address is in the range 8000
H
to BFFF
H
which
corresponds to A[15:14] = 10, the bank select circuit is invoked.
The bank addressing circuit only affects the upper four bits of the
external data bus. The top two A[17:16] are completely new, and
the next two A[15:14] are replacements for the processor A[15:
14] bits. Fig. 14 is a block diagram of the Bank Select circuitry.
Table 26
Page Base
Address (Hex)
Bank_Sel
3:0
Bank_Sel
3:0
Page Base
Address (Hex)
0000
0001
0010
0011
0100
0101
0110
0111
00000
04000
08000
0C000
10000
14000
18000
1C000
1000
1001
1010
1011
1100
*
1101
*
1110
*
1111
*
20000
24000
28000
2C000
30000
34000
38000
3C000
*
Refer to System Memory Map section for more details
Table 27
Non-Banked
Banked
Set to 11
Same as
Micro
Always
CSEPN
Bit 4
A[17:16]
A[15:14]
Chip Select
Bank Select register bits [3:0]
Table 28
相關(guān)PDF資料
PDF描述
ACE9050 System Controller and Data Modem Advance Information
ACFA-450 AM CERAMIC FILTERS
ACFA-455 AM CERAMIC FILTERS
ACFA-459 AM CERAMIC FILTERS
ACFA-468 AM CERAMIC FILTERS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ACE9050C/IW/FP1N 制造商:Microsemi Corporation 功能描述:PB FREE SYSTEM CONTROLLER & DATA MODEM - Bulk
ACE9050C/IW/FP1Q 制造商:Microsemi Corporation 功能描述:PB FREE SYSTEM CONTROLLER & DATA MODEM - Bulk
ace9050c/iw/fp8q 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
ace9050d/ig/gp1n 制造商:Microsemi Corporation 功能描述:CNTRLR AND DATA MODEM 100LQFP - Bulk 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
ACE9050D/IG/GP2N 制造商:Microsemi Corporation 功能描述:CNTRLR AND DATA MODEM 100LQFP - Bulk
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