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| 型號： | ACE9050 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | System Controller and Data Modem(為蜂窩式手機提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器) |
| 中文描述： | 系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器（為蜂窩式手機提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器） |
| 文件頁數(shù)： | 21/52頁 |
| 文件大?。?/td> | 366K |
| 代理商： | ACE9050 |
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ACE9050
21
The page addressing can access up to 16
3
16K pages per
Chip Select line in theory; however the original 6303 memory
map must also reside in the 256K of CSEPN memory space.
This is put to the top of the system memory map by the
ACE9050 and represents Pages 13 to 16. So, for example,
the 6303 address range C000
H
to FFFF
H
will access the same
memory location as 8000
to BFFF
with the bank select
register set at 0F
. This is useful when programming a FLASH
memory device, but care must be exercised in the addressing
of run time code. For the top four pages the system designer
must decide whether to access the area via its page address
or its direct (Root) address. For the original 6303 4 pages:
Page 1
(0000
H
-3FFF
H
) = Page 13 (30000
H
-33FFF
H
)
This must be used for ROOT ROM, as the code will jump
to 1800
after reset. This means the bottom 6K of the
page (0000
H
-17FF
H
) cannot be used unless it is
accessed via its banked address. It does allow the
maximum possible (42K) memory area to be configured
as Non Banked.
Page 2
(40000
-7FFF
) = Page 14 (340000
-37FFF
)
This page can either be used as Root, or banked.
Page 3
(8000
H
-BFFF
H
) = Page 15 (38000
H
-3BFFF
H
)
This page is banked by definition.
Page 4
(C000
-FFFF
) = Page 16 (30000H-3FFFF
)
The final page could either be accessed via it banked
address or Root address, however as this contains the
Interrupts it must be Root.
The designer can also allocate any of these or further
shadowed 16 pages to the CSE2N chip select. It is up to the
system designer whether to use unique pages for CSE2N or
shadow a ROM (CSEPN) page .
5. INTERRUPTS
The ACE9050 contains one nternal nterrupt port, one external
interrupt port and one I
2
C interrupt. This expands the one 6303
maskable interrupt (IRQN) into eight internal and two external
interrupts. The Interrupt control logic enables masking, reading
and resetting of the potential interrupt sources. Three registers
are associated with each of the two interrupt control ports,
IRQPRT 0, 1 and 2 for internal and IRQPRT 4, 5 and 6 for
external interrupts. Each Interrupt control port will generate an
Interrupt request line, as will the I
2
C interrupt. These three lines
are NORed together to produce the 6303 IRQN input. Fig. 16 is
a block diagram of the Interrupt Section.
If a source is not masked an interrupt will be generated and
the corresponding bit set in the Interrupt register. If it is masked
no interrupt will be generated and the correspondincg bit will not
get set in the interrupt register. Once an interrupt is generated,
it can be read in IRQPRT2, 6 or the I
2
C section. If both internal
and external interrupts are enabled the processor must read both
IRQPRT2 and 6; however, if only external or internal interrupts
are enabled the software need only read th corresponding
register. To reset the interrupt, a write to IRQPRT0 or 4 is
required with the correspondin bit set to 0. The interrupts sources
are not prioritised in the ACE9050. Handling the I
2
C interrupt is
covered separately in the I
2
C Interface description, Section 10.
Masking Interrupts
The IRQN input to the 6303 is a level sensitive maskable
interrupt line. This means that it is possible to enable and disable
all interrupts from the ACE9050 in the 6303. This is useful to
avoid nested interrupt situations.
If several interrupts are unmasked in the ACE9050, the
interrupt handler routine can disable all interrupt when it is
dealing with an interrupt via the 6303. If another valid interrupt
occurs during this time the IRQN line will be driven low by the
ACE9050. When the IRQN is enabled in the 6303 at the end of
processing, the first interrupt the 6303 will detect low IRQN line
and re-enter the interrupt handler routine. This will continue until
all pending interrup have been serviced when the IRQN line will
remain high. If more than one pending interrupt occurs the
software can prioritise its response, by the way the interrupt
handler is written.
The later interrupts must not be cleared in IRQPRT0, 1, 4 or
5 by the software until they have been serviced. The ACE9050
will not detect more that one pending interrupt from a given
source, i.e. it will not tell that two IRQ-WS have been missed, only
that an IRQ-WS interrupt has occured.
Internal Interrupt Control Port
The internal interrupt control port facilitates resetting, masking
and reading of seven potential internal interrupt sources via three
registers. Table 29 describes the possible sources.
Associated Registers
(Table 30)
IRQPRT0:
Internal Interrupt Reset Register
Writing a zero in a data bit of this register will reset the
corresponding interrupt source.
IRQPRT1:
Internal Interrupt Mask Register
A write to this register will determine the possible
source of interrupts. At reset all interrupts are masked
IRQPRT2:
Internal Interrupt Read register
A Read from this register will determine the interrupts
source.
Bit
7
6
5
3
2
1
0
IRQ-TX
IRQ-WS
IRQ-BI-SAT
IRQ-RX
IRQ-REC
IRQ-SEND
IRQ-TO
Modem: Data Transmitted
Modem: Received Word synch-
ronisation sequence
Modem: Busy Idle bit or SAT updated
Modem: Rx Data registers updated
ACE Serial Interface Received data
ACE Serial Interface Sent data
Time Out (ATO expired)
Name
Description
Table 29 Internal interrrupt sources
IRQPRT0
Bit
[7: 0]
Reset
Name
Description
0 = Reset
1 = No change
IRQPRT1
[7: 0]
Mask
0 = Reset and masked
1 = Enabled
[7: 5]
4
[3:0]
Source
-
Source
0 = Interrupt
1 = No Interrupt
Should be masked
0 = Interrupt
1 = No Interrupt
IRQPRT2
Table 30
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACE9050 | System Controller and Data Modem Advance Information |
| ACFA-450 | AM CERAMIC FILTERS |
| ACFA-455 | AM CERAMIC FILTERS |
| ACFA-459 | AM CERAMIC FILTERS |
| ACFA-468 | AM CERAMIC FILTERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACE9050C/IW/FP1N | 制造商:Microsemi Corporation 功能描述:PB FREE SYSTEM CONTROLLER & DATA MODEM - Bulk |
| ACE9050C/IW/FP1Q | 制造商:Microsemi Corporation 功能描述:PB FREE SYSTEM CONTROLLER & DATA MODEM - Bulk |
| ace9050c/iw/fp8q | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| ace9050d/ig/gp1n | 制造商:Microsemi Corporation 功能描述:CNTRLR AND DATA MODEM 100LQFP - Bulk 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| ACE9050D/IG/GP2N | 制造商:Microsemi Corporation 功能描述:CNTRLR AND DATA MODEM 100LQFP - Bulk |
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