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參數(shù)資料
| 型號： | ACE9050 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | System Controller and Data Modem(為蜂窩式手機提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器) |
| 中文描述： | 系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器（為蜂窩式手機提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器） |
| 文件頁數(shù)： | 42/52頁 |
| 文件大?。?/td> | 366K |
| 代理商： | ACE9050 |
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ACE9050
42
TCSR
6303 Timer Control Status Register
Register used to control and read the status of th 6303 Timer
block. Refer to ‘6303 Processor Unit’ section of Hitachi or
Motorola data book for full details .
ICR 6303
Input Capture register
16 bit read only register used to hold the value of the free running
counter captured when the proper transition of the ICN input
occurred. Refer to ‘6303 Processor Unit’ section or Hitachi or
Motorola data book for full details.
Detailed Operation
Once the IFC counter is set the next rising edge of the AFC/
RXDATA input pin will generate a negative transition on ICN.
The IFC counter will then count the required number of transitions
and create a positive edge on ICN at the end of the count period.
The program has to control the 6303 timer in such a way that
first the negative and then the positive transition of ICN is
captured. The software can then calculate the difference between
the two readings, which will give the elapsed time.
Programming Example
Initialise
(a) Set IFFREQ to the determine the required Count
(b) Reset STIFCN bit. This bit is reset by a hardware reset or by
writing 0. It is not reset by the counter finishing execution.
(c) Ensure the 6303 TCSR register is configured so as to
capture a falling edge on ICN.
Begin Count
(a) Write 1 to STIFCN
(b) Read the ICR after the negative transition on ICN
(c) Set TCSR register so as to capture a rising edge on ICN
(Within 5 or 45 ms)
End of Count
(a) When a capture has occurred the ICR register can be read.
Calculate
From the difference between the two ICR values captured,
the elapsed time for the count period can be calculated. It is then
possible to estimate the offset of the system crystal and cancel
out this error using the ACE9030 DACs.
If the crystal is off frequency it will have little effect on the timer
accuracy. It will however affect the main synthesiser as the error
is multiplied by the divider ratio set in the main synthesiser. The
absolute error is then mixed down to appear on the 54kHz
directly.
5. PULSE WIDTH MODULATOR
Two Pulse Width Modulators are available in the ACE9050.
These provide CMOS type outputs whose average high time can
be set by software. External components can be used to filter the
output and give a mean DC level. The values chosen for these
components depend on the ripple and response time required in
the application. Typical applications for such outputs are LCD
contrast control and battery charging control. The PWM outputs
are fed to output multiplexers; the corresponding external pin
function is selected by software.
The PWM circuits are designed to minimise the low frequency
components of the output wave form. The PWM works on a
254
μ
s cycle time, with 0·992
μ
s pulse duration. The number of
pulses is programmed using the appropriate register. The
hardware ensures that the pulses are distributed as evenly as
possible within a cycle. This is shown in Fig. 24 for some simple
programming examples.
With suitable external components the following formula can be
used to obtain the mean DC level of a PWM output:
V
MEAN
= (DAC[7:0]
4
256)
3
V
DD
External Pins
OUT2[1]/PWM1
Output (pin 98)
Selection for the source for this pin is made via the PWMlMUX
bit in PORT5. This pin is also described in the External Ports and
Multiplexer section.
OUT[2]/PWM2/LATCH[2]
Output (pin 81)
Selection for the source for this pin is made via the OUT2.2_SEL
bits in PORT5. This pin is also described in the External Ports and
Multiplexer section.
Associated Registers
Write
Register
DAC1 PORT
DAC2 PORT
Number of output pulses in a cycle
period
Number of output pulses in a cycle
period
Description
Bits
7:0
7:0
Table 94
Fig. 24 Pulse Width Generator output
NUMBER
LOADED
32
64
128
1
·
008MHz
CLOCK
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PDF描述 |
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| ACE9050 | System Controller and Data Modem Advance Information |
| ACFA-450 | AM CERAMIC FILTERS |
| ACFA-455 | AM CERAMIC FILTERS |
| ACFA-459 | AM CERAMIC FILTERS |
| ACFA-468 | AM CERAMIC FILTERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACE9050C/IW/FP1N | 制造商:Microsemi Corporation 功能描述:PB FREE SYSTEM CONTROLLER & DATA MODEM - Bulk |
| ACE9050C/IW/FP1Q | 制造商:Microsemi Corporation 功能描述:PB FREE SYSTEM CONTROLLER & DATA MODEM - Bulk |
| ace9050c/iw/fp8q | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| ace9050d/ig/gp1n | 制造商:Microsemi Corporation 功能描述:CNTRLR AND DATA MODEM 100LQFP - Bulk 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| ACE9050D/IG/GP2N | 制造商:Microsemi Corporation 功能描述:CNTRLR AND DATA MODEM 100LQFP - Bulk |
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