參數(shù)資料
型號: ACE9050
廠商: Mitel Networks Corporation
英文描述: System Controller and Data Modem(為蜂窩式手機提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器)
中文描述: 系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器(為蜂窩式手機提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器)
文件頁數(shù): 8/52頁
文件大?。?/td> 366K
代理商: ACE9050
ACE9050
8
Description
Symbol
Units
Turbo clock
Typ.
Max.
Min.
Normal clock
Typ.
Max.
Min.
t
ECLK
t
AD
V
WE
H
t
WE
H
AD
I
t
CS
L
WE
H
t
WE
L
WE
H
t
DA
V
WE
H
t
WE
H
DA
I
t
AD
V
DA
LZ
t
AD
V
CS
L
t
WE
H
CS
H
Cycle time
Address valid to end of Write
Address hold time
Chip enable set-up time
WE pulse width
Data valid set-up time
Data hold time
Address valid to data low Z
Address valid to chip select
WE high to CS high
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
395
63
390
173
177
60
203
0
66
496
420
72
415
181
183
225
4
72
427
93
425
184
192
239
9
105
835
125
825
363
365
120
451
0
127
992
853
140
840
364
368
473
5
140
862
151
860
371
371
487
10
163
Timing Cycle Conditions
Input clock frequency, XIN = 8·064MHz.
Worst case timings:
T
AMB
=
2
40
°
C to
1
85
°
C, V
DD
=
1
3·6V to
1
5·5V
Typical timings:
T
AMB
=
1
25
°
C, V
DD
=
1
3·75V
t
AD
V
CS
L
t
CS
L
WE
H
t
ECLK
t
AD
V
WE
H
t
WE
L
WE
H
t
WE
H
AD
I
t
WE
H
CS
H
t
AD
V
DA
LZ
t
DA
V
WE
H
t
WE
H
DA
I
ECLK
ADDR
CS
WEN
DATA
Write Cycle (Normal Mode)
Fig. 5 ACE9050 6303 Write cycle timing diagram
Table 4 ACE9050 6303 Write cycle timing
相關(guān)PDF資料
PDF描述
ACE9050 System Controller and Data Modem Advance Information
ACFA-450 AM CERAMIC FILTERS
ACFA-455 AM CERAMIC FILTERS
ACFA-459 AM CERAMIC FILTERS
ACFA-468 AM CERAMIC FILTERS
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