ACE9050
23
Bit
[1: 0]
[1: 0]
[1: 5]
Reset
Mask
Read
Name
Description
IRQPRT4
0 = Reset
1 = No change
IRQPRT5
0 = Masked
1 = Enabled
IRQPRT6
0 = Interrupted
1 = Not Interrupted
Table 32
OUT 2[6]
(pin 76),
OUT2[7]
(pin 79)
Output pins High Current inverting output pins. May be used for
LED or backlight drivers. Their state is set up via OUT_PORT2.
Upon reset OUT_PORT 2[7:6] are reset low. Due to the inverting
nature of the outputs this means OUT 2[7] and OUT 2[6] are high.
Associated Registers
IN_PORT1:
ACE9050 Input Port: Read Only
Bit
7
6
5
4
3
2
1
0
POWDET
SERV
-
INP1 [4]
INP1 [3]
INP1 [2]
INRQ1
INRQ0
Logic Level of TXPOW Input pin
Logic Level of SERV Input pin
Read back as 0
Logic Level of INP1 [4] pin
Logic Level of INP1 [3] pin
Logic Level of INP1 [2] pin
Logic Level of INRQ1 pin
Logic Level of INRQ0 pin
Name
Description
Table 33
Bit
7
6
5
4
3
2
1
0
OUTP2 [7]
OUTP2 [6]
OUTP2 [5]
OUTP2 [4]
OUTP2 [3]
OUTP2 [2]
OUTP2 [1]
High Current Inverting O/P
*
High Current Inverting O/P
*
Set to 0: Not used
Set to 0: Not used
Set to 0: Not used
O/P to multiplexer with PWM2 and Latch2)
O/P to multiplexer (with PWM1)
O/P when CPUCL disabled
Name
Description
OUT_PORT2:
ACE9050 Output Port: Read and Write
*
On reset, these bits are set low and the corresponding output pins
driven high.
Table 34
6. EXTERNAL PORTS AND MULTIPLEXER
The ACE9050 contains 2 external ports, addition to the 6303
Port1 and Port2 which a described in section 1 ‘ACE9050 6303R
Description’. One of the ports is an input register (IN_PORT1),
the other an output (OUT_PORT2). Both are 8-bit, but not all bits
are accessible from outside the ACE9050.
Two bits from OUT_PORT2 are fed to a multiplexer. This
enables multiple functions to share the same external pin, thus
reducing the overall pin count. The functions multiplexed with the
port are the Pulse Width Modulators and the ACE serial Interface
Latch2. Selection is made via the ACE9050 control Port 5.
Further I/O capability can be obtained by using the Keypad
interface as standard ports. This is described in the ‘Keypad
Interface’ section of the data sheet.
External Pins
INPUTS
INRQ1, INRQ0:
External Port and Interrupt Input (pins 70 & 71)
The logic level of these external inputs are read via
IN_ PORT1[1:0], regardless of whether these inputs are
configured to generate interrupts or not.
INP1[4], INP1[3], INP1[2]:
External Port Inputs (pins 54,53,52)
Uncommitted input. The logic level of these pins can be read
via IN_PORT1[4:2].
SERV
: Service Input (pin 74)
The state of the mode select line SERV can be read by
software via IN_PORT1. The function of SERV is described in
‘Modes Of Operation’ section.
TXPOW:
Power Detect input (pin 61)
The TXPOW input goes to the Watchdog and ATO block,
refer to ‘Autonomous Timeout’ section for more details. The state
of the input can be read via IN_PORT1.
OUTPUTS
OUTP2 [0]/CPUCL
OUT_PORT2[0] or CPUCL Clock (pin 94)
When the CPUCL Clock Output is disabled in the Clock
Generator this pin is driven by the OUT_PORT2 [0]. Refer to
‘Clock Generator’ section for details of the CPUCL function.
OUTP2 [1]/PWM1
(pin 98)
This pin can be either be driven from OUT_PORT2[1] or the
Pulse Width Modulator 1. The selection is made via Port5[0].
OUTP2 [2]/PWM2/Latch2
(pin 81)
This pin can be driven from: OUT_PORT 2[2], Pulse Width
Modulator 2 or ACE Serial Interface Latch2. The selection is
made via Port 5[5:4].
Table 36
Bit 0
0
1
Pulse width modulator 1
OUT_PORT2 [1] (Reset state)
OUT2 [1]/PWM1 pin function
PORT5 [0]:
PWM 1 MUX
Table 35
Bit 5
0
0
1
1
OUTP2 [2]/PWM2/LATCH2 pin function
Bit 5
0
1
0
1
OUT_PORT2 [2] (Reset state)
Pulse width modulator 2
ACE Serial Interface Latch 2
Not valid
PORT5 [5:4]:
OUTP2.2_SEL