參數(shù)資料
型號(hào)： ACE9050
廠商： Mitel Networks Corporation
英文描述： System Controller and Data Modem(為蜂窩式手機(jī)提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器)
中文描述： 系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器（為蜂窩式手機(jī)提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器）
文件頁(yè)數(shù)： 26/52頁(yè)
文件大?。?/td> 366K
代理商： ACE9050
ACE9050
26
SDA
SCL
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
D7
·
·
·
·
·
D1
D0
D0
1-7
8
9
1-7
8
9
1-7
8
9
STOP
CONDITION
START
CONDITION
S
P
D7
·
·
·
·
·
D1
Fig.19 I
2
C Data transfer
ACE9050 I
2
C
The ACE9050 I
2
C can operate in one of four modes:
1. Master Transmit
2. Master Receive
3. Slave Transmit
4. Slave Receive
The ACE9050 can operate in multi-Master systems (where
there is more than Master on the bus). The ACE9050 I
2
C will
perform bus arbitration and clock synchronisation. In a mobile
handset where the I
2
C is used to interface to a serial PROM and/
or an LCD display it would be sufficient to have the ACE9050 as
the sole Master.
The I
2
C interface consists of the SCL (clock) and SDA (data)
lines. These are multiplexed with the 6303 bidirectional Port1
pins to reduce the overall pin count. Selection is made via the
ACE9050 Port5.
The internal 6303 microprocessor interface consists of five 8-
bit memory mapped registers and a processor interrupt line. The
interrupt is connected to the 6303 IRQN interrupt, as are the
ACE9050 internal and external Interrupt ports.
External Pins
SCL/6303 Port 1 [4]
(pin 9)
Bi-directional pin, used for the I
2
C clock when selected. This
pin requires an external pull up resistor when used as SCL.. The
value of the pull up resistor depends on the system and I
2
C bus
implementation. Refer to the I
2
C bus specification. In a typical
system the resistor value would fall between 1k
and 20k
.
SDA/6303 Port 1 [3]
(pin 13)
Bidirectional pin, used for the I
2
C data when selected. This pin
requires an external pull up resistor when used as SDA. The
value of the resistor should be the same as the SCL line.
Associated Registers
SEL_I2C
Port 5 bit 2
Position
D7
D6
D5
D4
D3
D2
D1
D0
IEN
ENAB
STA
STP
IFLG
AAK
-
-
Bit
Description
Table 40
Interrupt Enable
Bus Enable
Master Mode Start
Master Mode Stop
Interrupt Flag
Assert Acknowledge
Read back only: 0
Read back only: 0
I2C_CNTR Control
Register Read/Write
This register is used to control the ACE9050 I
2
C. The program
can write and read from the register. The hardware can also
change the status of the bits in this register (see Table 40).
Note that this register is cleared to 00
H
when the I
2
C is reset.
IEN
Interrupt Enable
When IEN is set to 1 an interrupt will occur when the IFLG bit
is set. This will cause an interrupt on the 6303 IRQ. When IEN is
cleared to zero the I
2
C interrupt will be disabled.
Bit
2
SEL_I2C
0 = I
2
C Reset, P1 [4] and [3] selected
1 = I
2
C operational, SCL and SDA selected
Name
Description
Table 39
ENAB
Bus Enable
When ENAB = 1 the ACE9050 I
2
C will respond to calls to its
Slave address (SLA6-0) and to the general call address if bit
GCE in the I2C_ADDR register is set.
STA
Start Master Mode
When STA = 1 the ACE9050 I
2
C enters Master mode and will
send a START condition on the bus when the bus is free. If the
STA bit is set to 1 when already in Master mode and one or more
bytes have been transmitted then a repeated START condition
will be sent. If the STA bit is set to 1 when the ACE9050 I
2
C is
being accessed in Slave mode then the ACE9050 I
2
C will
complete the data transfer in Slave mode and then enter Master
mode when the bus has been released.
After the START condition has been sent this bit will be
automatically cleared.
STP
Stop Master Mode
When STP is set to 1 in Master mode then a STOP condition
is transmitted on the I
2
C bus. If the STP bit is set to 1 in Slave
mode then the ACE9050 I
2
C will behave as if a STOP condition
has been received, but no STOP condition will be transmitted on
the I
2
C bus. If both STA and STP bits are set the ACE9050 I
2
C
will first transmit the STOP condition (if in Master mode) then
transmit the START condition. The STP bit is automatically
cleared: writing a zero to this bit has no effect.
IFLG
Interrupt Flag
This bit gets set if an interrupt condition occurs in the I
2
C;
however an interrupt will only be generated if the Interrupt Enable
(IEN) is set.
An interrupt condition is defined as one of 26 of the possible
27 ACE9050 I
2
C states being entered. The only state that does
not set IFLG is state F8
H
. Refer to STAT register for more
information on the I
2
C states.
When IFLG is high then the low period of the I
2
C bus clock line,
SCL, is stretched and the data transfer is suspended.
When IFLG is reset to zero the interrupt is reset and the I
2
C
clock line released.
相關(guān)PDF資料
PDF描述
ACE9050 System Controller and Data Modem Advance Information
ACFA-450 AM CERAMIC FILTERS
ACFA-455 AM CERAMIC FILTERS
ACFA-459 AM CERAMIC FILTERS
ACFA-468 AM CERAMIC FILTERS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ACE9050C/IW/FP1N 制造商:Microsemi Corporation 功能描述:PB FREE SYSTEM CONTROLLER & DATA MODEM - Bulk
ACE9050C/IW/FP1Q 制造商:Microsemi Corporation 功能描述:PB FREE SYSTEM CONTROLLER & DATA MODEM - Bulk
ace9050c/iw/fp8q 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
ace9050d/ig/gp1n 制造商:Microsemi Corporation 功能描述:CNTRLR AND DATA MODEM 100LQFP - Bulk 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
ACE9050D/IG/GP2N 制造商:Microsemi Corporation 功能描述:CNTRLR AND DATA MODEM 100LQFP - Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*