參數(shù)資料
型號(hào)： ACE9050
廠商： Mitel Networks Corporation
英文描述： System Controller and Data Modem(為蜂窩式手機(jī)提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器)
中文描述： 系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器（為蜂窩式手機(jī)提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器）
文件頁(yè)數(shù)： 41/52頁(yè)
文件大小： 366K
代理商： ACE9050
ACE9050
41
PROGRAMMING
Programming Constraints
The programming of the interface is relatively straightforward
when used with the ACE Chipset. However, the following
constraints apply:
(a) To activate a Latch 3 transfer on the ACEBus, the
STR_WIDTH register must be written to with a non-zero
value prior to writing to LSICOM3 [7] (GO) set.
(b) After writing to LSICOM3 with the GO bit set, registers
LSICOM0 to 3 must not be written for 25
μ
s or until an IRQ-
SEND Interrupt has been generated.
(c) After writing to LSICOM3 with the GO and ANS bits set,
LSICOM0 to 3 must not be written to until 6 clock cycles after
an IRQ-SEND. LSICOM3 cannot be written to with bit 7 (GO)
set until 55
μ
s or the IRQ-REC interrupt has been generated.
This is because the DTFG will contain the slave data until this
time.
(d) A value greater than 0 must not be written to the STR_WIDTH
register preceding a LATCH0, 1, 2 transfer or a Latch3
transfer with the SynthBus.
(e) The ACEBus and the SynthBus cannot be used
simultaneously.
Programming Sequences
ACEBus Transfers
Latch 0 Data Transfer
(1) Write Data to LSICOM0,1 and 2
(2) Write to LSICOM3 control word:
(3) Service IRQ-SEND interrupt if enabled
Latch 1 Data Transfer
(a) Without answer request
(1) Write Data to LSICOM0, 1 and 2
(2) Write LSICOM3 Control word:
GO
1
CL
1
ANS
0
0
0
0
L1
0
L0
1
GO
1
CL
1
ANS
0
0
0
0
L1
1
L0
0
(3) Service IRQ-SEND interrupt if enabled
(b) With answer request
(1) Write Data to LSICOM 0, 1 and 2
(2) Write LSICOM 3 Control word:
GO
1
CL
1
ANS
1
0
0
0
L1
1
L0
0
(3) Service IRQ-SEND interrupt if enabled
(4) Wait for IRQ-REC interrupt
(5) Read data from LSICOM 4, 5 and 6
Latch 3 Data Transfer (ACEBus)
(1) Write Data to LSICOM 0 to 2
(2) Write Strobe Width to STR_WIDTH(non-zero value)
(3) Write LSICOM 3 Control word:
GO
1
CL
1
ANS
0
0
0
0
L1
0
L0
0
(4) Service IRQ-SEND interrupt if enabled
The Strobe width will be a minimum of 100
μ
s, However data
can be transmitted to the other slave units during the Latch3 high
time. Alternatively the Latch3 may be terminated prematurely by
writing 0 into the STR_WIDTH register. This may only be done
after the IRQ-SEND nterrupt, to ensure the atch s not terminated
prematurely.
The ONRAD bit (PORT 3 [6]) can be used to keep the Latch
3 line high. Care must be taken when enabling Latch3 in this way
so that spurious data is not clocked into the synthesiser. By
setting the STR_WIDTH register to a suitably large value and
enabling ONRAD before the STR_WIDTH time expires, the
Latch 3 line can be permanently asserted. The STR_WIDTH
time begins when the data transfer has completed.
SynthBus Transfers
Latch 3 Data Transfer
(1) Write Data to LSICOM 0 to 2
(2) Write LSICOM3 Control word:
GO
1
CL
0
ANS
0
0
1
L2
0
0
0
L3
(3) Service IRQ-SEND interrupt if enabled
Latch 2 Data Transfer
(1) Write Data to LSICOM 0 to 2
(2) Write LSICOM 3 Control word:
GO
1
CL
0
ANS
0
0
0
L2
1
0
0
L3
(3) Service IRQ-SEND interrupt if enabled
4. IFC COUNTER
The IFC counter is used as part of the Automatic Frequency
Compensation loop, in conjunction with 6303 timer. The IFC
counts a predetermined number of periods of the AFC_IN/
RXDATA signal. By timing this duration the frequency of the input
can be determined. In a system using the ACE chipset this input
frequency will be 54kHz. The Number of periods counted can be
either 256 or 2432. This will give measurement times over a
period of approximately 5ms or 45ms when using the ACE
chipset. Other input frequencies are possible, but would give
different time periods and thus accuracy could be affected.
External Signals
AFC/RXDATA
Input (pin 60)
This signal also feeds to the AMPS/TACS modem. This pin
can be directly connected to the AFCOUT pin of the ACE9030,
when this device is being used.
ICN
Output (pin 77)
This output is used in emulation mode only. It is output of the
IFC counter, which should be connect to the Emulator 6303
PORT2 [0]. It is internally connected to the ACE9050 6303.
Associated Registers
Register
Description
Bit
STIFCN
PORT 3 [5]
IFFREQ
P0RT 3 [0]
Reset counter
*
Enable counter
2432 counts
256 counts
0
1
0
1
*
The counter must be reset before it can be enabled
Table 93
相關(guān)PDF資料
PDF描述
ACE9050 System Controller and Data Modem Advance Information
ACFA-450 AM CERAMIC FILTERS
ACFA-455 AM CERAMIC FILTERS
ACFA-459 AM CERAMIC FILTERS
ACFA-468 AM CERAMIC FILTERS
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