ACE9050
44
Input Port
The Keyboard interface has four inputs. These inputs can
also be used as general inputs. The upper four bits of this port are
hard wired and provide a means of identifying the present variant
of the ACE9050.
External Pins
KPI[3:0]
4-bit Input port (pins 66 to 69)
The state of this input port can be obtained by reading the
respective bits in the internal register KEYP.
Associated Registers
KEYP
[7:0]
Read
Keypad input port register
Description
Level
0
1
Receive signal absent
Receive signal present
Table 102
A typical source for the receive signal strength would be the
RSSI output from the IF Strip. However this will need to be
compared to a predefined level and the logical output fed to the
ACE9050. The ACE9030 provides an ADC, programmable
threshold register and comparator for this purpose via RXCD.
TXPOW
TX power level input (pin 61)
Digital input to monitor the presence of a Transmitted signal,
as shown in Table 103.
Description
Level
0
1
Transmit signal absent
Transmit signal present
Table 103
A typical source for the transmit signal presence would be a
detector in the TX path. However this will need to be compared
to a predefined level and the logical output fed to the ACE9050.
The ACE9030 provides two Op Amps that may be used for this
purpose. One may be used as a buffer/amp and the other as a
comparator in conjunction with a DAC, which is also on the
ACE9030. The level of TXPOW can be directly determined via
IN Port1[7], POWDET.
POFFN
Power Off output (pin 85)
This pin is intended to be used to control external power
regulators for the phone. It is reset low by an MRN reset. The
software and the ATO then control the state of POFFN:
The software can set the state of POFFN directly via
Port 3[4].
The ATO reset can only drive POFFN output low.
POFFN is not cleared by a Watchdog reset, so that this type
of reset will not power down the phone. When in Service mode
the ATO Reset is disabled and the IROM code sets POFFN to
logic 1.
Associated Registers
RESATO
Reset ATO: Write
Description
Bits
[7:4]
[3:0]
Chip Identity code (See Table 101)
Reads the level of the associated input on KPI [3:0]
Table 100
Identity code
Description
Bits
7
6
5
4
Read back 0
Read back 0
Read back1
Read back 0
Table 101
Bit
-
Description
Write access resets the 30s ATO timer.
Table 104
Bit
4
UPOFFN
0 = POFFN output set low
1 = POFFN output set high
Name
Table 105
Description
UPOFFN
Port 3
Bit 4 of this register sets the state of the POFFN output, as shown
in Table 105.
8. AUTONOMOUS TIMEOUT (ATO)
The Autonomous Time Out circuit (ATO) is provided to
facilitate an automatic power down of the phone in the event of
the phone entering an illegal transmitting state. The ATO block
requires external functions to implement its intended operation.
The ATO monitors the status of the RXCD and TXPOW
inputs; in a typical system these will indicate the presence of
received and transmitted signals, respectively. If a transmitted
signal is detected, without the presence of a received signal the
ATO circuitry can change the state of the output pin, POFFN.
This should be used to remove power from the phone system via
external power control circuitry.
The main block in the ATO is a 30-second counter. It is reset
by an accepted processor write to the RESATO register. The
state of the external inputs RXCD and TXPOW determine
whether the processor access is accepted. If the processor does
not attempt to access the register, or access is blocked for a
period of 30 seconds, the ATO Timer expires and an ATO reset
occurs.
External Pins
RXCD
Receive Path Carrier Detect Input (pin 100)
Digital input to indicate the presence of a carrier in the receiver
part of the Radio as shown in Table 102.