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| 型號： | AD14060LBF-4 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CMOS 32BIT 308CQFP |
| 產(chǎn)品培訓(xùn)模塊： | SHARC Processor Overview |
| 標(biāo)準包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | 主機接口，連接端口，串行端口 |
| 時鐘速率： | 40MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 2MB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 308-CBQFP |
| 供應(yīng)商設(shè)備封裝： | 308-CQFP（52x52） |
| 包裝： | 托盤 |
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Quad-SHARC
DSP Multiprocessor Family
AD14060/AD14060L
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
PERFORMANCE FEATURES
ADSP-21060 core processor ( × 4)
480 MFLOPS peak, 320 MFLOPS sustained
25 ns instruction rate, single-cycle
instruction execution—each of four processors
16 Mbit shared SRAM (internal to SHARCs)
4 gigawords addressable off-module memory
Twelve 40 Mbyte/s link ports (3 per SHARC)
Four 40 Mbit/s independent serial ports
(one from each SHARC)
One 40 Mbit/s common serial port
5 V and 3.3 V operation
32-bit single precision and 40-bit extended
precision IEEE floating point data formats, or
32-bit fixed point data format
IEEE JTAG Standard 1149.1 test access port and
on-chip emulation
PACKAGING FEATURES
308-lead ceramic quad flatpack (CQFP)
2.05" (52 mm) body size
Cavity up or down, configurable
Low profile, 0.160" height
Hermetic
25 Mil (0.65 mm) lead pitch
29 grams (typical)
θJC = 0.36°C/W
FUNCTIONAL BLOCK DIAGRAM
CPA
SPORT 1
EBOOT,
LBOOT,
BM
S
CS
TIM
EXP
LINK
1
LINK
3
LINK
4
IRQ
2–
0
FLAG
2,
0
EM
U
CLKIN
R
ESET
SPOR
T
0
TCK,
TMS,
TRST
FLAG
1
FLAG
3
SHARC_A
(ID2–0 = 1)
LINK 0
LINK 2
LINK 5
TDO
LINK 0
LINK 2
LINK 5
TDI
LINK 0
LINK 2
LINK 5
TDI
EBOOT,
LBOOT,
BM
S
EM
U
CLKIN
R
ESET
SPOR
T
0
TRST
TMS,
TCK,
TRST
TMS,
TCK,
FLAG
1
FLAG
3
,
CPA
SPORT 1
TDO
SHARC_D
(ID2–0 = 4)
CS
TIM
EXP
LINK
1
LINK
3
LINK
4
IRQ
2–0
FLAG
2,
0
AD14060/AD14060L
CPA
SPORT 1
TDI
LINK 0
LINK 2
LINK 5
TDO
EBOOT,
LBOOT,
BM
S
EM
U
CLKIN
R
ESET
SPOR
T
0
FLAG
1
FLAG
3
TDI
CPA
SHARC_C
(ID2–0 = 3)
SHARC_B
(ID2–0 = 2)
CS
TIM
EXP
LINK
1
LINK
3
LINK
4
IRQ
2–0
FLAG
2,
0
SHARC BUS (ADDR31–0, DATA47–0, MS3-0, RD, WR, PAGE, ADRCLK,
SW, ACK, SBTS, HBR, HBG, REDY, BR6–1, RPBA, DMAR1.2, DMAG1.2)
EBOOT,
LBOOT,
BM
S
EM
U
CLKIN
R
ESET
SPOR
T
0
TCK,
TMS,
TRST
FLAG
1
FLAG
3
TDO
CS
TIM
EXP
LINK
1
LINK
3
LINK
4
IRQ
2–
0
FLAG
2,
0
00667-001
Figure 1.
GENERAL DESCRIPTION
The AD14060/AD14060L Quad-SHARC is the first in a family
of high performance DSP multiprocessor modules. The core of
the multiprocessor is the ADSP-21060 DSP microcomputer. The
AD14060/AD14060L has the highest performance-to-density
and lowest cost-to-performance ratios of any in its class. It is
ideal for applications requiring higher levels of performance
and/or functionality per unit area.
The AD14060/AD14060L takes advantage of the built-in
multiprocessing features of the ADSP-21060 to achieve
480 peak MFLOPS with a single chip type in a single package.
The on-chip SRAM of the DSPs provides 16 Mbits of on-
module shared SRAM. The complete shared bus (48 data,
32 address) is also brought off-module for interfacing with
expansion memory or other peripherals.
The ADSP-21060 link ports are interconnected to provide direct
communication among the four SHARCs, as well as high speed
off-module access. Internally, each SHARC has a direct link port
connection. Externally, each SHARC has a total of 120 Mbytes/s
link port bandwidth.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and
optimized signal routing lengths and separation. The fully
tested and ready-to-insert multiprocessor also significantly
reduces board space.
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