Type1 Function TDI I/S Test Data Input (JTAG). Provides ser" />
參數(shù)資料
型號： AD14060LBF-4
廠商： Analog Devices Inc
文件頁數(shù)： 27/48頁
文件大?。?/td> 0K
描述： IC DSP CMOS 32BIT 308CQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 主機(jī)接口，連接端口，串行端口
時鐘速率： 40MHz
非易失內(nèi)存： 外部
芯片上RAM： 2MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 308-CBQFP
供應(yīng)商設(shè)備封裝： 308-CQFP（52x52）
包裝： 托盤
AD14060/AD14060L
Rev. B | Page 33 of 48
Pin
Type1
Function
TDI
I/S
Test Data Input (JTAG). Provides serial data for the boundary scan logic chain starting at SHARC_A. TDI has a 20 k
internal pull-up resistor.
TDO
O
Test Data Output (JTAG). Serial scan output of the boundary scan chain path, from SHARC_D.
TRST
I/A
Test Reset (JTAG) (common to all SHARCs). Resets the test state machine. TRST must be asserted (pulsed low) after
power-up or held low for proper operation of the AD14060/AD14060L. TRST has a 20 k internal pull-up resistor.
EMU (O/D)
O
Emulation Status (common to all SHARCs). Must be connected to the ADSP-2106x EZ-ICE target board connector
only.
VDD
P
Power Supply. Nominally 5.0 V dc for 5 V devices or 3.3 V dc for 3.3 V devices (26 pins).
GND
G
Power Supply Return (28 pins).
FLAG3 is connected internally, common to SHARC_A, B, C, and D.
ID pins are hardwired internally as shown in Figure 1.
1 I = input; P = power supply; (A/D) = active drive; O = output; S = synchronous; (O/D) = open drain; G = ground; A = asynchronous; T = three-state, when SBTS is
asserted, or when the AD14060/AD14060L is a bus slave.
2 Link Ports 0, 2, and 5 are connected internally, as described in the Li
section.
nk Port I/O
3 Three-statable only in EPROM boot mode (when BMS is an output).
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