參數(shù)資料
型號: AD14060LBF-4
廠商: Analog Devices Inc
文件頁數(shù): 29/48頁
文件大?。?/td> 0K
描述: IC DSP CMOS 32BIT 308CQFP
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標準包裝: 1
系列: SHARC®
類型: 浮點
接口: 主機接口,連接端口,串行端口
時鐘速率: 40MHz
非易失內(nèi)存: 外部
芯片上RAM: 2MB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 308-CBQFP
供應(yīng)商設(shè)備封裝: 308-CQFP(52x52)
包裝: 托盤
AD14060/AD14060L
Rev. B | Page 35 of 48
DATA
ADDR
DATA
ADDR
BLOCK
1
DATA
ADDR
DATA
ADDR
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
BLOCK
0
I/O PROCESSOR
TIMER
INSTRUCTION
CACHE
32 x 48-BIT
JTAG
TEST AND
EMULATION
DUAL-PORTED SRAM
EXTERNAL
PORT
HOST PORT
ADDR BUS
MUX
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
24
CORE PROCESSOR
DAG1
8 x 4 x 32
DAG2
8 x 4 x 24
32
PROGRAM
SEQUENCER
MULTIPLIER
BARREL
SHIFTER
ALU
DATA
REGISTER
FILE
16 x 40-BIT
48
40/32
7
32
48
4
6
36
BUS
CONNECT
(PX)
IOD
48
IOA
17
SERIAL PORTS
(2)
LINK PORTS
(6)
DMA
CONTROLLER
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS, AND
DATA BUFFERS
00667-003
Figure 21. ADSP-21060 Processor Block Diagram (Core of AD10460)
CLKIN
RESET
RPBA
CPA
BOOTSELECT A
BOOTSELECT BCD
DMAR1, 2
DMAG1, 2
SPORT0
FLAG1
JTAG
1× CLOCK
SHARC_D
LINKS 1, 3, AND 4;
IRQ2–0;
FLAGS 2 AND 0;
TIMEXP,
SPORT1
SHARC_C
LINKS 1, 3, AND 4;
IRQ2–0;
FLAGS 2 AND 0;
TIMEXP,
SPORT1
RD
WR
ACK
MS3-0
PAGE
SBTS
SW
ADRCLK
CS
HBR
HBG
REDY
BR1–6
DATA47–0
ADDR31–0
SHARC_A
LINKS 1, 3, AND 4;
IRQ2–0;
FLAGS 2 AND 0;
TIMEXP,
SPORT1
SHARC_B
LINKS 1, 3, AND 4;
IRQ2–0;
FLAGS 2 AND 0;
TIMEXP,
SPORT1
AD14060/AD14060L
(QUAD PROCESSOR CLUSTER)
SYSTEM EXPANSION
00667-005
Figure 22. Complete Shared Memory Multiprocessing System
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