參數(shù)資料
型號(hào)： AD14060LBF-4
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/48頁(yè)
文件大小： 0K
描述： IC DSP CMOS 32BIT 308CQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 主機(jī)接口，連接端口，串行端口
時(shí)鐘速率： 40MHz
非易失內(nèi)存： 外部
芯片上RAM： 2MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 308-CBQFP
供應(yīng)商設(shè)備封裝： 308-CQFP（52x52）
包裝： 托盤
AD14060/AD14060L
Rev. B | Page 18 of 48
DMA HANDSHAKE
These specifications describe the three DMA handshake modes. In all three modes, DMAR is used to initiate transfers. For handshake
mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled by the
ADDR31-0, RD, WR, SW, PAGE, MS3-0, ACK, and DMAG signals. For paced master mode, the data transfer is controlled by ADDR31-0, RD,
WR, MS3-0, and ACK (not DMAG). For paced master mode, the memory read—bus master, memory write—bus master, and synchronous
read/write—bus master timing specifications for ADDR31-0, RD, WR, MS3-0, SW, PAGE, DATA47-0, and ACK also apply.
Table 15. Specifications
5 V
3.3 V
Parameter
Min
Max
Min
Max
Unit
Timing Requirements:
tSDRLC
DMARx Low Setup before CLKIN1
5
ns
tSDRHC
DMARx High Setup before CLKIN1
5
ns
tWDR
DMARx Width Low (Nonsynchronous)
6
ns
tSDATDGL
Data Setup after DMAGx Low2
9 + 5 DT/8
ns
tHDATIDG
Data Hold after DMAGx High
2
ns
tDATDRH
Data Valid after DMAGx High2
15.5 + 7 DT/8
ns
tDMARLL
DMAGx Low Edge to Low Edge
23 + 7 DT/8
ns
tDMARH
DMAGx Width High
6
ns
Switching Characteristics:
tDDGL
DMAGx Low Delay after CLKIN
9 + DT/4
16 + DT/4
9 + DT/4
16 + DT/4
ns
tWDGH
DMAGx High Width
6 + 3 DT/8
ns
tWDGL
DMAGx Low Width
12 + 5 DT/8
ns
tHDGC
DMAGx High Delay after CLKIN
2 DT/8
+7 DT/8
2 DT/8
+7 DT/8
ns
tVDATDGH
Data Valid before DMAGx High3
7.5 + 9 DT/16
ns
tDATRDGH
Data Disable after DMAGx High4
1
+7.5
1
+7.5
ns
tDGWRL
WR Low before DMAGx Low
0.5
+2.5
0.75
+2.5
ns
tDGWRH
DMAGx Low before WR High
9.5 + 5 DT/8 + W
ns
tDGWRR
WR High before DMAGx High
0.5 + DT/16
3.5 + DT/16
0.5 + DT/16
3.5 + DT/16
ns
tDGRDL
RD Low before DMAGx Low
0.25
+2.5
0
2.5
ns
tDRDGH
RD Low before DMAGx High
11 + 9 DT/16 + W
ns
tDGRDR
RD High before DMAGx High
0
3.5
0
3.5
ns
tDGWR
DMAGx High to WR, RD, DMAGx Low
4.5 + 3 DT/8 + HI
ns
tDADGH
Address/Select Valid to DMAGx High
16 + DT
ns
tDDGHA
Address/Select Hold after DMAGx High
1.5
ns
W = number of wait states specified in WAIT register × tCK.
HI = tCK, if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise, HI = 0.
1 Required only for recognition in the current cycle.
2 tSDATDGL is the data setup requirement, if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data
can be driven tDATDRH after DMARx is brought high.
3 tVDATDGH is valid, if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = 7.5 + 9 DT/16 + (n × tCK), where n
equals the number of extra cycles that the access is prolonged.
4 See the
section for the calculation of hold times given capacitive and dc loads.
System Hold Time Calculation Example
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