參數(shù)資料
型號(hào)： AD6636
廠商： Analog Devices, Inc.
元件分類： 數(shù)字上／下變頻
英文描述： 150 MSPS Wideband Digital Down-Converter (DDC)
中文描述： 150MSPS的寬帶數(shù)字下變頻器（DDC）
文件頁(yè)數(shù)： 23/72頁(yè)
文件大小： 1629K
代理商： AD6636
AD6636
Figure 26 is a block diagram of the peak detector logic. The
MSR contains the absolute magnitude of the peak detected by
the peak detector logic.
Rev. 0 | Page 23 of 72
POWER MONITOR
HOLDING
REGISTER
LOAD
MAGNITUDE
STORAGE
REGISTER
LOAD
COMPARE
A>B
TO
MEMORY
MAP
FROM
MEMORY
MAP
FROM
INPUT
PORTS
LOAD
CLEAR
0
IS COUNT = 1
DOWN
COUNTER
TO
INTERRUPT
CONTROLLER
POWER MONITOR
PERIOD REGISTER
Figure 26. ADC Input Peak Detector Block Diagram
Mean Power Mode (Control Bits 01)
In this mode, the magnitude of the input port signal is
integrated (by adding an accumulator) over a programmable
time period (given by AMPR) to give the integrated magnitude
of the input signal. This mode is set by programming Logic 1 in
the power monitor function select bits of the power monitor
control register for each individual input port. The 24-bit
AMPR, representing the period over which integration is
performed, must be programmed before activating this mode.
After enabling this mode, the value in the AMPR is loaded into
a monitor period timer, and the countdown is started
immediately. The 15-bit magnitude of input signal is right-
shifted by nine bits to give 6-bit data. This 6-bit data is added to
the contents of a 24-bit holding register, thus performing an
accumulation. The integration continues until the monitor
period timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the value
in the MSR is transferred to the power-monitor holding register
(after some formatting), which can be read through the
microport or the serial port. The monitor period timer is
reloaded with the value in the AMPR, and the countdown is
started. Also, the first input sample signal magnitude is updated
in the MSR, and the accumulation continues with the
subsequent input samples. If the interrupt is enabled, an
interrupt is generated, and the interrupt status register is
updated when the AMPR reaches a count of 1. Figure 27
illustrates the mean power-monitoring logic.
The value in the MSR is a floating-point number with 4 MSBs
and 20 LSBs. If the 4 MSBs are EXP and the 20 LSBs are MAG,
the value in dBFS can be decoded using the following equation:
Mean Power
= 10 log
)
(
20
2
2
EXP
MAG
0
POWER MONITOR
HOLDING
REGISTER
ACCUMULATOR
TO
MEMORY
MAP
FROM
MEMORY
MAP
FROM
INPUT
PORTS
LOAD
CLEAR
LOAD
IS COUNT = 1
DOWN
COUNTER
TO
INTERRUPT
CONTROLLER
POWER MONITOR
PERIOD REGISTER
Figure 27. ADC Input Mean Power-Monitoring Block Diagram
Threshold Crossing Mode (Control Bits 10)
In this mode of operation, the magnitude of the input port
signal is monitored over a programmable time period (given by
AMPR) to count the number of times it crosses a certain
programmable threshold value. This mode is set by program-
ming Logic 1x (where x is a don’t care bit) in the power-monitor
function select bits of the power monitor control register for
each individual input port. Before activating this mode, the user
needs to program the 24-bit AMPR and the 10-bit upper
threshold register for each individual input port. The same
upper threshold register is used for both power monitoring and
gain control (see the ADC Gain Control section).
After entering this mode, the value in the AMPR is loaded into
a monitor period timer, and the countdown is started. The
magnitude of the input signal is compared to upper threshold
register (programmed previously) on each input clock cycle. If
register, then the MSR register is incremented by 1. The initial
value of the MSR is set to zero. This comparison and increment
of the MSR register continues until the monitor period timer
reaches a count of 1.
When the monitor period timer reaches a count of 1, the value
in the MSR is transferred to the power monitor holding register,
which can be read through the microport or the serial port. The
monitor period timer is reloaded with the value in the AMPR,
and the countdown is started. The MSR register is also cleared
to a value of zero. If interrupts are enabled, an interrupt is
generated, and the interrupt status register is updated when the
AMPR reaches a count of 1. Figure 28 illustrates the threshold
crossing logic. The value in the MSR is the number of samples
that have an amplitude greater than the threshold register.
0
POWER MONITOR
HOLDING
REGISTER
COMPARE
A > B
UPPER
THRESHOLD
REGISTER
COMPARE
A > B
TO
MEMORY
MAP
FROM
MEMORY
MAP
FROM
MEMORY
MAP
FROM
INPUT
PORTS
LOAD
CLEAR
LOAD
IS COUNT = 1
DOWN
COUNTER
TO
INTERRUPT
CONTROLLER
POWER MONITOR
PERIOD REGISTER
B
A
Figure 28. ADC Input Threshold Crossing Block Diagram
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