- 您現(xiàn)在的位置：買賣IC網 > PDF目錄373891 > AD6636 (Analog Devices, Inc.) 150 MSPS Wideband Digital Down-Converter (DDC) PDF資料下載
參數(shù)資料
| 型號： | AD6636 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字上／下變頻 |
| 英文描述： | 150 MSPS Wideband Digital Down-Converter (DDC) |
| 中文描述： | 150MSPS的寬帶數(shù)字下變頻器（DDC） |
| 文件頁數(shù)： | 67/72頁 |
| 文件大小： | 1629K |
| 代理商： | AD6636 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁當前第67頁第68頁第69頁第70頁第71頁第72頁
AD6636
AGC Pole Location <7:0>
This 8-bit register is used to define the open-loop filter pole
location P. Its value can be set from 0 to 0.996 in steps of 0.0039.
This value of P is updated in the AGC loop each time the AGC
is initialized. This open-loop pole location directly impacts the
closed-loop pole locations, as explained in the Automatic Gain
Control section.
AGC Desired Level <7:0>
This register contains the desired signal level or desired clipping
level, depending on operational mode. This desired request level
(R) can be set in dB from 0 to 23.99 in steps of 0.094 dB. The
request level (R) in dB should be converted to a register setting
using the following formula:
Rev. 0 | Page 67 of 72
Register Value
=
round
×
64
)
log
20
10
R
AGC Loop Gain2 <7:0>
This 8-bit register is used to define the second possible open-
loop gain, K
2
. Its value can be set from 0 to 0.996 in steps of
0.0039. This value of K
2
is updated each time the AGC is
initialized. When the magnitude-of-error signal in the loop is
greater than the AGC error threshold, then K
2
is used by the
loop. K
2
is updated only when the AGC is initialized.
AGC Loop Gain1 <7:0>
This 8-bit register is used to define the open-loop gain K
1
. Its
value can be set from 0 to 0.996 in steps of 0.0039. This value of
K is updated in the AGC loop each time the AGC is initialized.
When the magnitude-of-error signal in the loop is less than the
AGC error threshold, then K
1
is used by the loop. K
1
is updated
only when the AGC is initialized.
I Path Signature Register <15:0>
This 16-bit signature register is for the I path of the channel
logic. The signature register records data on the networks that
leave the channel logic, just before entering the second data
router.
Q Path Signature Register <15:0>
This 16-bit signature register is for the Q path of the channel
logic. The signature register records data on the networks that
leave the channel logic, just before entering the second data
router.
BIST Control <23:0>
<15>: Disable Signature Generation Bit. When this bit is active
high, the signature registers do not produce a pseudorandom
output value, but instead directly load the 24-bit input data.
When this bit is cleared, the signature register produces a
pseudorandom output for every clock cycle that it is active. See
the User-Configurable Built-In Self-Test (BIST) section for
details.
<14:0>: BIST Timer Bits. The <14:0> bits of this register form a
15-bit word that is loaded into the BIST timer. After loading the
BIST timer, the signature register is enabled for operation while
the timer is actively counting down. (See the User-Configurable
Built-In Self-Test (BIST) section.)
OUTPUT PORT REGISTER MAP
This part of the memory map deals with the output data and
controls for parallel output ports.
Parallel Port Output Control <31:0>
<23>: Port C Append RSSI Bit. When this bit is set, an RSSI
word is appended to every I/Q output sample, irrespective of
whether the RSSI word is updated in the AGC. When this bit is
cleared, an RSSI word is appended to an I/Q output sample only
when the RSSI word is updated. The RSSI word is not output for
subsequent I/Q samples until the next time the RSSI is updated
in the AGC.
<22>: Port C, Data Format Bit. When this bit is set, the port is
configured for 8-bit parallel I/Q mode. When cleared, the port is
configured for 16-bit interleaved I/Q mode. See the Parallel Port
Output section for details.
<21>: Port C, AGC 5 Enable Bit. When this bit is set, AGC 5 data
(I/Q data) is output on parallel Output Port C (data bus). When
this bit is cleared, AGC 5 data does not appear on Output
Port C.
<20>: Port C, AGC 4 Enable Bit. Similar to Bit <21> for AGC 4.
<19>: Port C, AGC 3 Enable Bit. Similar to Bit <21> for AGC 3.
<18>: Port C, AGC 2 Enable Bit. Similar to Bit <21> for AGC 2.
<17>: Port C, AGC 1 Enable Bit. Similar to Bit <21> for AGC 1.
<16>: Port C, AGC 0 Enable Bit. Similar to Bit <21> for AGC 0.
<15>: Port B Append RSSI Bit. When this bit is set, an RSSI
word is appended to every I/Q output sample, irrespective of
whether or not the RSSI word is updated in the AGC. When this
bit is cleared, an RSSI word is appended to an I/Q output sample
only when the RSSI word is updated. The RSSI word is not
output for subsequent I/Q samples until the next time the RSSI
is updated in the AGC.
<14>: Port B, Data Format Bit. When this bit is set, the port is
configured for 8-bit parallel I/Q mode. When this bit is cleared,
the port is configured for 16-bit interleaved I/Q mode. See the
Parallel Port Output section.
<13>: Port B, AGC 5 Enable Bit. When this bit is set, AGC 5 data
(I/Q data) is output on parallel output Port A (data bus). When
this bit is cleared, AGC 5 data does not appear on output Port C.
相關PDF資料 |
PDF描述 |
|---|---|
| AD6636BBCZ1 | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BC | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636CBCZ1 | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636PCB | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD664(中文) | Monolithic 12-Bit Quad DAC(單片12位四D/A轉換器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD6636BBC | 制造商:Analog Devices 功能描述:Digital Down Converter 256-Pin CSP-BGA |
| AD6636BBCZ | 功能描述:IC DIGITAL DWNCONV 6CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應商設備封裝:12-QFN-EP（3x3） |
| AD6636BBCZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BC | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 150MSPS Wideband Digital Down-Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。