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參數(shù)資料
| 型號： | AD6636 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字上／下變頻 |
| 英文描述： | 150 MSPS Wideband Digital Down-Converter (DDC) |
| 中文描述： | 150MSPS的寬帶數(shù)字下變頻器（DDC） |
| 文件頁數(shù)： | 33/72頁 |
| 文件大?。?/td> | 1629K |
| 代理商： | AD6636 |
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AD6636
Because this filter is nondecimating, the input and output rates
are both same and equal to one of the following:
Rev. 0 | Page 33 of 72
f
MRCF
=
f
HB2
,
if HB2 is bypassed
f
MRCF
=
2
HB2
f
,
if HB2 is not bypassed
If
f
PLLCLK
is the PLL clock and if
2
PLLCLK
TAPS
MRCF
f
N
f
≥
×
then half of the PLL clock can be used for processing (power
savings). Otherwise, the PLL clock should be used.
Bypass
The MRCF filter can be used in normal operation or bypassed
using the MRCF bypass bit in the MRCF control register. When
the filter is bypassed, the output of the filter is the same as the
input of the filter. Bypassing the MRCF filter when not required
results in power savings.
Scaling
The output of the MRCF filter can be scaled by using the 2-bit
MRCF scaling word in the MRCF control register. Table 18
shows the valid values for the 2-bit word and their correspond-
ing settings.
Table 18. MRCF Scaling Factor Settings
MRCF Scale Word [1:0]
00
01
10
11
Scaling Factor
18.06 dB attenuation
12.04 dB attenuation
6.02 dB attenuation
No scaling, 0 dB
DECIMATING RAM COEFFICIENT FILTER (DRCF)
Following the MRCF is the programmable DRCF FIR filter.
This filter can calculate up to 64 asymmetrical filter taps or up
to 128 symmetrical filter taps. The filter is also capable of a
programmable decimation rate of from 1 to 16. A flexible
coefficient offset feature allows loading multiple filters into the
coefficient RAM and changing the filters on the fly. The
decimation phase feature allows a polyphase implementation,
where multiple AD6636 channels are used for processing a
single carrier.
The DRCF filter has 20-bit input and output data and 14-bit
coefficient data. The number of filter taps to calculate is
programmable and is set in the DRCF taps register. The value
of the number of taps minus one is written to this register.
For example, a value of 19 in the register corresponds to
20 filter taps.
The decimation rate is programmable using the 4-bit DRCF
decimation rate word in the DRCF control register. Again, the
value written is the decimation rate minus one.
Bypass
The DRCF filter can be used in normal operation or bypassed
using the DRCF bypass bit in the DRCF control register. When
the DRCF filter is bypassed, no scaling is applied and the output
of the filter is the same as the input to the DRCF filter.
Scaling
The output of the DRCF filter can be scaled using the 2-bit
DRCF scaling word in the DRCF control register. Table 19 lists
the valid values for the 2-bit word and their corresponding
settings.
Table 19. DRCF Scaling Factor Settings
DRCF Scale Word [1:0]
00
01
10
11
Scaling Factor
18.06 dB attenuation
12.04 dB attenuation
6.02 dB attenuation
No scaling, 0 dB
Symmetry
The DRCF filter does not require symmetrical filters. However,
if the filter is symmetrical, then the symmetry bit in the DRCF
control register should be set. When this bit is set, only half of
the impulse response needs to be programmed into the DRCF
coefficient memory registers. For example, if the number of
filter taps is equal to 15 or 16 and the filter is symmetrical, then
only eight coefficients need to be written into the coefficient
memory. Because a total of 64 taps can be written into the
memory registers, the DRCF can perform 64 asymmetrical filter
taps or 128 symmetrical filter taps.
Coefficient Offset
More than one set of filter coefficients can be loaded into
coefficient RAM at any given time (given sufficient RAM
space). The coefficient offset can be used in this case to access
the two or more different filters. By changing the coefficient
offset, the filter coefficients being accessed can be changed on
the fly. This decimal offset value is programmed in the DRCF
coefficient offset register. When this value is changed during the
calculation of a particular output data sample, the sample
calculation is completed using the old coefficients, and the new
coefficient offset from the next data sample calculation is used.
Decimation Phase
When more than one channel of AD6636 is used to process one
carrier, polyphase implementation of corresponding channels’
DRCF or CRCF is possible using the decimation phase feature.
This feature can be used only under certain conditions. The
decimation phase is programmed using the 4-bit DRCF
decimation phase word of the DRCF control register.
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