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參數(shù)資料
| 型號(hào)： | AD6636 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字上／下變頻 |
| 英文描述： | 150 MSPS Wideband Digital Down-Converter (DDC) |
| 中文描述： | 150MSPS的寬帶數(shù)字下變頻器（DDC） |
| 文件頁數(shù)： | 32/72頁 |
| 文件大?。?/td> | 1629K |
| 代理商： | AD6636 |
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AD6636
The filter input sample rate is the same as the FIR2 filter output
rate and is given by one of the following equations:
Rev. 0 | Page 32 of 72
f
HB2
= f
FIR2
=
f
HB1
,
if HB1 is bypassed
f
HB2
= f
FIR2
=
2
HB1
f
,
if HB1 is not bypassed
where:
f
FIR1
is the input rate of the FIR1 filter.
f
HB1
is the input rate of the HB1 filter.
The input to the filter has a maximum of 75 MHz. The
maximum output rate when not bypassed is 37.5 MHz.
The filter has a ripple of 0.00075 dB and rejection of 81 dB. For
an alias rejection of 81 dB, the alias-protected bandwidth is 33%
of the filter input sample rate. The bandwidth of the filter for a
ripple of 0.00075 dB is the same as alias-protected bandwidth,
due to the nature of half-band filters. The 3 dB bandwidth of
this filter is 47% of the filter input sample rate. For example, if
the sample rate into the filter is 25 MHz, then the alias-
protected bandwidth of the HB2 filter is 8.25 MHz (33% of
25 MHz). If the bandwidth of the required carrier is greater
than 8.25 MHz, then HB2 might not be useful.
0
FRACTION OF HB2 INPUT SAMPLE RATE
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
d
0.01
–19.99
–29.99
–9.99
–39.99
–49.99
–60.00
–70.00
–80.00
–90.00
–100.00
–110.00
–120.00
–90
0.66
0.34
FIR2 + HB2
RESPONSE
Figure 36. Composite Response of FIR1 and HB1 filters to Their Input Rates
INTERMEDIATE DATA ROUTER
Following the FIR-HB cascade filters is the intermediate data
router. This data router consists of muxes that allow the I and Q
data from any channel front end (input port + NCO + CIC +
FIR-HB) to be processed by any channel back end (MRCF +
DRCF + CRCF). The choice of channel front end is made by
programming a 3-bit MRCF data select word in the MRCF
control register. The valid values for this word and their
corresponding settings are listed in Table 17.
Table 17. Data Router Select Settings
MRCF Data Select [2:0]
000
001
010
011
1x0
1x1
Data Source
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Allowing different channel back ends to select different channel
front ends is useful in the polyphase implementation of filters.
When multiple AD6636 channels are used to process a single
carrier, a single-channel front end feeds more than one channel
back end. After processing through the channel back ends (RCF
filters), the data is interleaved back from all the polyphased
channels.
MONO-RATE RAM COEFFICIENT FILTER (MRCF)
The MRCF is a programmable sum-of-products FIR filter. This
filter block comes after the first data router and before the
DRCF and CRCF programmable filters. It consists of a
maximum of eight taps with 6-bit programmable coefficients.
Note that this block does not decimate and is used as a helper
filter for the DRCF and CRCF filters that follow in the signal
chain.
The number of filter taps that are to be calculated is program-
mable using the 3-bit number-of-taps word in the MRCF
control register of the channel under consideration. The 3-bit
word programmed is one less than the number of filter taps.
The coefficients themselves are programmed in eight MRCF
coefficient memory registers for individual channels. The input
and output data to the block are both 20-bit.
Symmetry
Though the MRCF filter does not require symmetrical filters, if
the filter is symmetrical, then the symmetry bit in the MRCF
control register should be set. When this bit is set, only half of
the impulse response needs to be programmed into the MRCF
coefficient memory registers. For example, if the number of
filter taps is equal to five or six and the filter is symmetrical,
then only three coefficients need to be written into the
coefficient memory. For both symmetrical and asymmetrical
filters, the number of filter taps is limited to eight.
Clock Rate
The MRCF filter runs on an internal high speed PLL clock. This
clock rate can be as high as 200 MHz. If the half clock rate bit in
the MRCF control register is set, then only half the PLL clock
rate is used (maximum of 100 MHz). This results in power
savings, but can only be used if certain conditions are met.
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