參數(shù)資料
型號(hào)： AD6636
廠商： Analog Devices, Inc.
元件分類(lèi)： 數(shù)字上／下變頻
英文描述： 150 MSPS Wideband Digital Down-Converter (DDC)
中文描述： 150MSPS的寬帶數(shù)字下變頻器（DDC）
文件頁(yè)數(shù)： 56/72頁(yè)
文件大?。?/td> 1629K
代理商： AD6636
AD6636
8-Bit Hex
Address
0x97
Rev. 0 | Page 56 of 72
Byte 3
Open<15:13>, CRCF Control Register<12:0>
Byte 2
Byte 1
Open <7:6>, CRCF
Coefficient Offset<5:0>
Open <7:6>, CRCF
Final Address<5:0>
Byte 0
Open<7>, CRCF Taps
<6:0>
Open <7:6>, CRCF Start
Address<5:0>
8-Bit Hex
Address
0x94
0x9B
Open<15:0>
0x98
0x9F
0xA3
0xA7
0xAB
Open<7:0>
Open<15:11>, AGC Control Register<10:0>
Open<15:12>, AGC Update Decimation<11:0>
Open<15:12>, AGC Error Threshold <11:0>
Open<23:20>, CRCF Coefficient Memory <19:0>
0x9C
0xA0
0xA4
0xA8
AGC Hold-Off Register<15:0>
Open<15:12>, AGC Signal Gain <11:0>
Open<7:6>, AGC Average
Samples<5:0>
AGC Loop Gain2 <7:0>
AGC Pole Location
<7:0>
AGC Loop Gain1 <7:0>
0xAF
0xB3
0xB7
0xBB
Output Port Register Map—Addresses 0xBC to 0xE7
0xBF
Open<7:0>
0xC3
Open<15:0>
0xC7
AGC0, I Output<15:0> (read only)
0xCB
AGC1, I Output <15:0> (read only)
0xCF
AGC2, I Output <15:0> (read only)
0xD3
AGC3, I Output <15:0> (read only)
0xD7
AGC4, I Output <15:0> (read only)
0xDB
AGC5, I Output <15:0> (read only)
0xDF
Open<15:12>, AGC0 RSSI Output<11:0> (read only)
0xE3
Open<15:12>, AGC2 RSSI Output<11:0> (read only)
0xE7
Open<15:12>, AGC4 RSSI Output<11:0> (read only)
Open<7:0>
Open<7:0>
Open<7:0>
Open <15:0>
AGC Desired Level<7:0>
BIST I Path Signature Register<23:0> (read-only, default 0xAD6636)
BIST Q Path Signature Register<23:0> (read-only, default 0xAD6636)
BIST Control <15:0>
0xAC
0xB0
0xB4
0xB8
0xBC
0xC0
0xC4
0xC8
0xCC
0xD0
0xD4
0xD8
0xDC
0xE0
0xE4
Parallel Port Output Control <23:0>
Open<15:10>, Output Port Control <9:0>
AGC0, Q Output <15:0> (read only)
AGC1, Q Output <15:0> (read only)
AGC2, Q Output <15:0> (read only)
AGC3, Q Output <15:0> (read only)
AGC4, Q Output <15:0> (read only)
AGC5, Q Output <15:0> (read only)
Open<15:12>, AGC1 RSSI Output<11:0> (read only)
Open<15:12>, AGC3 RSSI Output<11:0> (read only)
Open<15:12>, AGC5 RSSI Output<11:0> (read only)
GLOBAL REGISTER MAP
Chip I/O Access Control Register <7:0>
<7>: Synchronous Microport Bit. When this bit is set, the
microport assumes that its controls signals (such as R/W, DS,
and CS,) are synchronous to the CPUCLK. When cleared,
asynchronous control signals are assumed, and the microport
control signals are resynchronized with CPUCLK inside the
AD6636 part. Synchronous microport (when bit is set) has the
advantage of requiring a fewer number of clock cycles for
read/write access.
<6>: This bit is open.
<5:2>: Chip ID Bits. The chip ID bits are used to compare
against the chip ID input pins, enabling or disabling I/O access
for this specific chip. When more than one AD6636 part is
sharing the microport, different CHIPID pins can be used to
differentiate among the parts. A particular part gives I/O access
only when the CHIPID pins have the same value as these chip
ID bits.
<1>: This bit is open.
<0>: Byte Mode Bit. The byte mode bit selects the bit width for
the microport operation. Table 30 shows details.
Table 30. Microport Data Bus Width Selection
Chip Access Control
Register <0>
0 (default)
1
Microport Data Bus Bit Width
8-bit mode, using D<7:0>
16-bit mode, using D<15:0>
Channel I/O Access Control Register <5:0>
These bits enable/disable the channel I/O access capability.
<5>: Channel 5 Access Bit. When the Channel 5 access bit is set
to Logic 1, any I/O write operation (from either the microport
or the serial port) that addresses a register located within the
channel register map updates the Channel 5 registers. Similarly,
for a read operation, the contents of the desired address in the
channel register map are output when this bit is set to Logic 1.
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