- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373891 > AD6636 (Analog Devices, Inc.) 150 MSPS Wideband Digital Down-Converter (DDC) PDF資料下載
參數(shù)資料
| 型號： | AD6636 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字上／下變頻 |
| 英文描述： | 150 MSPS Wideband Digital Down-Converter (DDC) |
| 中文描述： | 150MSPS的寬帶數(shù)字下變頻器（DDC） |
| 文件頁數(shù)： | 49/72頁 |
| 文件大?。?/td> | 1629K |
| 代理商： | AD6636 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁當(dāng)前第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
AD6636
SPI Mode Write Operation
In SPI mode, the SCLK runs only when data is being trans-
ferred, so no external framing is necessary. The SPI serial mode
supports slave operations only. Input data on SDI pin is
registered on the rising edge of SCLK and, therefore, the DSP or
master device should be set to change data on the falling edge of
SCLK. All input and output transfers take place in 8-bit
transactions.
Rev. 0 | Page 49 of 72
For a write operation, the user must write two 8-bit instruction
words to the serial port to instruct the AD6636 internal control
logic about the data to be written. The first instruction word is
an address location. If the MSBFIRST pin is Logic 1, this
address is the ending address; if it is Logic 0, this address
corresponds to the starting address. The second instruction
word contains a 1-bit read/write indicator (MSB bit: 1 = read,
0 = write), followed by a 7-bit field to indicate the number of
address locations to write (N).
Following the instruction words are the N write operations
(each one byte long), where N is the number of address
locations to write. After each write cycle, the internal address is
incremented (MSBFIRST = 0) or decremented (MSBFIRST =
1). In this case, MSBFIRST indicates the first bit coming out of
or into the SPI port as well as which byte is written first (most
significant byte of the N-byte transfer).
For example, consider writing Addresses 0x01 to 0x07 of
AD6636 register map, when operating in SPI mode and
MSBFIRST = 0. The instruction words are Addresses 0x01 and
0x07 (MSB = 0 for write). The following seven write cycles
transfer one byte at a time sequentially into Addresses 0x01 to
0x07, in that order. The instruction words and data should be
written with LSB first.
If the example is for MSBFIRST = 1, then the instruction words
are 0x07 (Address 7) and 0x07 (number of addresses to write).
The data corresponds to Addresses 0x07 to 0x01, in that order.
The instruction words and data are MSB first.
SPI Mode Read Operation
Data on the SDO pin is shifted out on the positive edge of
SCLK. Therefore, the DSP or other master device should
register data on the falling edge of SCLK. All input and output
transfers take place in 8-bit transactions. The SDO pin is high
impedance when data is not being output.
Each read cycle consists of SCS going low, eight clock cycles
generated on SCLK pin, followed by SCS pulled high. Data
corresponding to the addresses to be read is transferred out on
the SDO pin and is registered by the master device on the
falling edge. The data is MSB first or LSB first based on the
status of MSBFIRST pin.
For example, consider reading Addresses 0x01 to 0x07 of the
AD6636 register map, when operating in SPI mode and
MSBFIRST = 0. The instruction words are Addresses 0x01 and
0x87 (MSB = 1 for read). The following seven read cycles
transfer one byte at a time, sequentially out of Addresses 0x01 to
0x07, in that order. The instruction words should be written
LSB first, and data comes out on the SDO with the LSB first.
If the example is for MSBFIRST = 1, then the instruction words
are 0x07 (Address 7) and 0x87 (MSB = 1 for read, followed by
the number of address locations to read). The data coming out
on SDO corresponds to Addresses 0x07 to 0x01, in that order.
The instruction words are written MSB first, and data comes
out on the SDO with MSB first.
SCLK
SCS
SMODE
SDI
MODE
t
SSCS
t
HSI
D0
D1
D2
D3
D4
D5
D6
D7
t
SSI
t
HSCS
LOGIC 1
LOGIC 0
0
Figure 44. SPI Write to the AD6636 Serial Port and Transfer of 1-Byte Data to Internal Registers
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD6636BBCZ1 | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BC | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636CBCZ1 | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636PCB | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD664(中文) | Monolithic 12-Bit Quad DAC(單片12位四D/A轉(zhuǎn)換器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6636BBC | 制造商:Analog Devices 功能描述:Digital Down Converter 256-Pin CSP-BGA |
| AD6636BBCZ | 功能描述:IC DIGITAL DWNCONV 6CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3） |
| AD6636BBCZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BC | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 150MSPS Wideband Digital Down-Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。