參數(shù)資料
型號(hào): ADSP-BF504BCPZ-4F
廠商: Analog Devices Inc
文件頁(yè)數(shù): 53/80頁(yè)
文件大?。?/td> 0K
描述: IC CCD SIGNAL PROCESSOR 88LFCSP
視頻文件: Blackfin? BF50x Processor Family
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類型: 定點(diǎn)
接口: CAN,EBI/EMI,I²C,IrDA,PPI,SPI,SPORT,UART/USART
時(shí)鐘速率: 400MHz
非易失內(nèi)存: 閃存(16MB)
芯片上RAM: 68kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.29V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 88-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 88-LFCSP(12x12)
包裝: 托盤(pán)
Rev. A
|
Page 57 of 80
|
July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
ADC—TIMING SPECIFICATIONS
ADC—ABSOLUTE MAXIMUM RATINGS
Stresses above those listed in Table 51 may cause permanent
damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above
those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Table 50. Serial Data Interface1
Parameter
Specification
Unit
Test Conditions / Comments
fADSCLK
2
2 Minimum ADSCLK for specified performance; with slower ADSCLK frequencies, performance specifications apply typically.
1/32
MHz min/max
tCONVERT
14 × tADSCLK
ns max
tADSCLK = 1/fADSCLK
437.5
ns max
fADSCLK = 32 MHz, fSAMPLE = 2 MSPS; AVDD, DVDD = 5 V
560.0
ns max
fADSCLK = 25 MHz, fSAMPLE = 1.56 MSPS; AVDD, DVDD = 3 V
583.3
ns max
fADSCLK = 24 MHz, fSAMPLE = 1.5 MSPS; AVDD, DVDD = 2.7 V
tQUIET
30
ns min
Minimum time between end of serial read and next falling edge of CS
t2
18/23
ns min
CS to ADSCLK setup time; VDD = 5 V/3 V
t3
15
ns max
Delay from CS until DOUTA and DOUTB are three-state disabled
t4
3
3 The time required for the output to cross 0.4 V or 2.4 V.
27/36
ns max
Data access time after ADSCLK falling edge, VDD = 5 V/3 V
t5
0.45 tADSCLK
ns min
ADSCLK low pulse width
t6
0.45 tADSCLK
ns min
ADSCLK high pulse width
t7
5/10
ns min
ADSCLK to data valid hold time, VDD = 5 V/3 V
t8
15
ns max
CS rising edge to DOUTA, DOUTB, high impedance
t9
30
ns min
CS rising edge to falling edge pulse width
t10
5/35
ns min/max
ADSCLK falling edge to DOUTA, DOUTB, high impedance
Table 51. Absolute Maximum Ratings
Parameter
Rating
AVDD, DVDD to AGND
–0.3 V to +7 V
DVDD to DGND
–0.3 V to +7 V
VDRIVE to DGND
–0.3 V to DVDD
VDRIVE to AGND
–0.3 V to AVDD
AVDD to DVDD
–0.3 V to +0.3 V
AGND to DGND
–0.3 V to +0.3 V
Analog Input Voltage to AGND
–0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND
–0.3 V to +7 V
Digital Output Voltage to GND
–0.3 V to VDRIVE + 0.3 V
VREF to AGND
–0.3 V to AVDD + 0.3 V
Input Current to Any ADC Pin
Except Supplies1
1 Transient currents of up to 100 mA will not cause latch up.
±10 mA
Storage Temperature Range
Junction Temperature Under Bias
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