參數(shù)資料
型號： ADSP-BF504BCPZ-4F
廠商： Analog Devices Inc
文件頁數(shù)： 59/80頁
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 88LFCSP
視頻文件： Blackfin? BF50x Processor Family
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點(diǎn)
接口： CAN，EBI/EMI，I²C，IrDA，PPI，SPI，SPORT，UART/USART
時鐘速率： 400MHz
非易失內(nèi)存： 閃存（16MB）
芯片上RAM： 68kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.29V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 88-LFCSP（12x12）
包裝： 托盤
Rev. A
|
Page 62 of 80
|
July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
When the ADC starts a conversion (see Figure 63 (ADC Con-
version Phase)), SW3 opens and SW1 and SW2 move to
Position B, causing the comparator to become unbalanced. Both
inputs are disconnected once the conversion begins. The con-
trol logic and the charge redistribution DACs are used to add
and subtract fixed amounts of charge from the sampling capaci-
tor arrays to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code.
The output impedances of the sources driving the VIN+ and VIN–
pins must be matched; otherwise, the two inputs will have dif-
ferent settling times, resulting in errors.
Analog Input Structure
the equivalent circuit of the analog input structure of the ADC
in differential/pseudo differential mode. In single-ended mode,
VIN is internally tied to AGND. The four diodes provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signals never exceed the supply rails by
more than 300 mV. This causes these diodes to become for-
ward-biased and starts conducting into the substrate. These
diodes can conduct up to 10 mA without causing irreversible
damage to the part.
Switches Closed) are typically 4 pF and can primarily be attrib-
uted to pin capacitance. The resistors are lumped components
made up of the on resistance of the switches. The value of these
resistors is typically about 100
Ω. The C2 capacitors are the
ADC’s sampling capacitors with a capacitance of 45 pF typically.
For ac applications, removing high frequency components from
the analog input signal is recommended by the use of an RC
low-pass filter on the relevant analog input pins with optimum
values of 47
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of THD that can be
tolerated.
The THD increases as the source impedance increases and per-
shows a graph of the THD vs. the analog input signal frequency
for different source impedances in single-ended mode, while
Impedances, Differential Mode) shows the THD vs. the analog
input signal frequency for different source impedances in differ-
ential mode.
Voltages) shows a graph of the THD vs. the analog input fre-
quency for various supplies while sampling at 2 MSPS. In this
case, the source impedance is 47
Ω.
Figure 63. ADC Conversion Phase
Figure 64. Equivalent Analog Input Circuit,
Conversion Phase—Switches Open, Track Phase—Switches Closed
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VIN+
VIN–
VREF
VDD
C1
D
VIN+
R1 C2
VDD
C1
D
VIN–
R1 C2
Figure 65. THD vs. Analog Input Frequency for Various
Source Impedances, Single-Ended Mode
INPUT FREQUENCY (kHz)
600
0
200
100
400
300
500
THD
(dB)
–50
–60
–55
–65
–70
–75
–80
–85
–90
FSAMPLE = 1.5MSPS
VDD = 3V
RANGE = 0V TO VREF
RSOURCE = 300
RSOURCE = 0
RSOURCE = 10
RSOURCE = 47
RSOURCE = 100
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