參數(shù)資料
型號(hào)： ADSP-BF504BCPZ-4F
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 62/80頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 88LFCSP
視頻文件： Blackfin? BF50x Processor Family
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點(diǎn)
接口： CAN，EBI/EMI，I²C，IrDA，PPI，SPI，SPORT，UART/USART
時(shí)鐘速率： 400MHz
非易失內(nèi)存： 閃存（16MB）
芯片上RAM： 68kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.29V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 88-LFCSP（12x12）
包裝： 托盤
Rev. A
|
Page 65 of 80
|
July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
to make use of the full dynamic range of the part. A dc input is
applied to the VIN– pin. The voltage applied to this input pro-
vides an offset from ground or a pseudo ground for the VIN+
input. The benefit of pseudo differential inputs is that they sepa-
rate the analog input signal ground from the ADC’s ground
allowing dc common-mode voltages to be cancelled.
The typical voltage range for the VIN– pin, while in pseudo dif-
ferential mode, is shown in Figure 74 (VIN– Input Voltage Range
vs. VREF in Pseudo Differential Mode with VDD = 3 V) and
Figure 75 (VIN– Input Voltage Range vs. VREF in Pseudo Differ-
ential Mode with VDD = 5 V). Figure 76 (Pseudo Differential
Mode Connection Diagram) shows a connection diagram for
pseudo differential mode.
Analog Input Selection
The analog inputs of the ADC can be configured as single-
ended or true differential via the SGL/DIFF logic pin, as shown
tion). If this pin is tied to a logic low, the analog input channels
to each on-chip ADC are set up as three true differential pairs. If
this pin is at logic high, the analog input channels to each on-
chip ADC are set up as six single-ended analog inputs. The
required logic level on this pin needs to be established prior to
the acquisition time and remain unchanged during the conver-
sion time until the track-and-hold has returned to track. The
track-and-hold returns to track on the 13th rising edge of
ADSCLK after the CS falling edge (see Figure 87 (Serial Inter-
face Timing Diagram)). If the level on this pin is changed, it will
be recognized by the ADC; therefore, it is necessary to keep the
same logic level during acquisition and conversion to avoid cor-
rupting the conversion in progress.
Ended Configuration) the SGL/DIFF pin is set at logic high for
the duration of both the acquisition and conversion times so the
analog inputs are configured as single ended for that conversion
(Sampling Point A). The logic level of the SGL/DIFF changed to
low after the track-and-hold returned to track and prior to the
Figure 73. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal
into a Differential Unipolar Signal
Figure 74. VIN- Input Voltage Range vs. VREF in
Pseudo Differential Mode with VDD = 3 V
20k
220k
2 × VREF p–p
27
V+
V–
V+
V–
GND
2.5V
3.75V
1.25V
2.5V
3.75V
1.25V
VIN+
ADC
1
VIN–
440
220
0.47μF
1ADDITIONAL PINS OMITTED FOR CLARITY.
220
10k
A
V
REF
(DCAPA/DCAPB)
VREF (V)
3.0
0
0.5
1.0
1.5
2.0
2.5
V
IN–
(V)
1.0
0.8
0.4
0.6
0.2
–0.2
0
–0.4
TA = 25°C
Figure 75. VIN– Input Voltage Range vs. VREF in
Pseudo Differential Mode with VDD = 5 V
Figure 76. Pseudo Differential Mode Connection Diagram
VREF (V)
5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V
IN–
(V)
2.5
2.0
1.5
1.0
0.5
0
–0.5
TA = 25°C
DC INPUT
VOLTAGE
VREF
p–p
VREF (DCAPA/DCAPB)
VIN+
ADC
1
VIN–
0.47μF
1ADDITIONAL PINS OMITTED FOR CLARITY.
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