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參數(shù)資料
| 型號： | ADSP-BF504BCPZ-4F |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 64/80頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 88LFCSP |
| 視頻文件： | Blackfin? BF50x Processor Family |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點(diǎn) |
| 接口： | CAN，EBI/EMI，I²C，IrDA，PPI，SPI，SPORT，UART/USART |
| 時鐘速率： | 400MHz |
| 非易失內(nèi)存： | 閃存（16MB） |
| 芯片上RAM： | 68kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.29V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 88-LFCSP（12x12） |
| 包裝： | 托盤 |
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Rev. A
|
Page 67 of 80
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July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Serial Interface Voltage Drive
The ADC also has a VDRIVE feature to control the voltage at
which the serial interface operates. VDRIVE allows the ADC to
easily interface to both 3 V and 5 V processors. For example, if
the ADC was operated with a AVDD/DVDD of 5 V, the VDRIVE pin
could be powered from a 3 V supply, best ADC performance
low voltage digital processors. Therefore, the ADC could be
used with the 2 × VREF input range, with a AVDD/DVDD of 5 V
while still being able to serial interface to 3 V digital I/O parts.
ADC—MODES OF OPERATION
The mode of operation of the ADC is selected by controlling the
(logic) state of the CS signal during a conversion. There are
three possible modes of operation: normal mode, partial power-
down mode, and full power-down mode. After a conversion is
initiated, the point at which CS is pulled high determines which
power-down mode, if any, the device enters. Similarly, if already
in a power-down mode, CS can control whether the device
returns to normal operation or remains in power-down. These
modes of operation are designed to provide flexible power man-
agement options. These options can be chosen to optimize the
power dissipation/throughput rate ratio for differing applica-
tion requirements.
Normal Mode
This mode is intended for applications needing fastest through-
put rates because the user does not have to worry about any
power-up times with the ADC remaining fully powered at all
times. Figure 80 (Normal Mode Operation) shows the general
diagram of the operation of the ADC in this mode.
The conversion is initiated on the falling edge of CS, as
described in the ADC—Serial Interface section. To ensure that
the part remains fully powered up at all times, CS must remain
low until at least 10 ADSCLK falling edges have elapsed after the
falling edge of CS. If CS is brought high any time after the 10th
ADSCLK falling edge but before the 14th ADSCLK falling edge,
the part remains powered up, but the conversion is terminated
and DOUTA and DOUTB go back into three-state. Fourteen serial
clock cycles are required to complete the conversion and access
the conversion result. The DOUT line does not return to three-
state after 14 ADSCLK cycles have elapsed, but instead does so
when CS is brought high again. If CS is left low for another 2
ADSCLK cycles (for example, if only a 16 ADSCLK burst is
available), two trailing zeros are clocked out after the data. If CS
is left low for a further 14 (or16) ADSCLK cycles, the result
from the other ADC on board is also accessed on the same DOUT
line, as shown in Figure 88 (Reading Data from Both ADCs on
Interface section.
Once 32 ADSCLK cycles have elapsed, the DOUT line returns to
three-state on the 32nd ADSCLK falling edge. If CS is brought
high prior to this, the DOUT line returns to three-state at that
point. Therefore, CS may idle low after 32 ADSCLK cycles until
it is brought high again sometime prior to the next conversion
(effectively idling CS low), if so desired, because the bus still
returns to three-state upon completion of the dual result read.
Once a data transfer is complete and DOUTA and DOUTB have
returned to three-state, another conversion can be initiated after
the quiet time, tQUIET, has elapsed by bringing CS low again
(assuming the required acquisition time is allowed).
Partial Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be per-
formed at a high throughput rate, and the ADC is then powered
Figure 78. Straight Binary Transfer Characteristic
Figure 79. Twos Complement Transfer Characteristic with
VREF ± VREF Input Range
000...000
111...111
1LSB = VREF/4096
1LSB
VREF – 1LSB
ANALOG INPUT
ADC
CODE
0V
000...001
000...010
111...110
111...000
011...111
NOTE
1. VREF IS EITHER VREF OR 2 × VREF.
100...000
011...111
1LSB = 2
u V
REF/4096
+VREF – 1 LSB
–VREF + 1LSB VREF – 1LSB
ANALOG INPUT
ADC
CODE
100...001
100...010
011...110
000...001
000...000
111...111
Figure 80. Normal Mode Operation
ADSCLK
LEADING ZEROS + CONVERSION RESULT
CS
DOUTA
DOUTB
114
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