- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19397 > ADSP-BF504BCPZ-4F (Analog Devices Inc)IC CCD SIGNAL PROCESSOR 88LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | ADSP-BF504BCPZ-4F |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 65/80頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 88LFCSP |
| 視頻文件： | Blackfin? BF50x Processor Family |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點(diǎn) |
| 接口： | CAN，EBI/EMI，I²C，IrDA，PPI，SPI，SPORT，UART/USART |
| 時(shí)鐘速率： | 400MHz |
| 非易失內(nèi)存： | 閃存（16MB） |
| 芯片上RAM： | 68kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.29V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 88-LFCSP（12x12） |
| 包裝： | 托盤 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)當(dāng)前第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)
Rev. A
|
Page 68 of 80
|
July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
down for a relatively long duration between these bursts of sev-
eral conversions. When the ADC is in partial power-down, all
analog circuitry is powered down except for the on-chip refer-
ence and reference buffer.
To enter partial power-down mode, the conversion process
must be interrupted by bringing CS high anywhere after the sec-
ond falling edge of ADSCLK and before the 10th falling edge of
ADSCLK, as shown in Figure 81 (Entering Partial Power-Down
Mode). Once CS is brought high in this window of ADSCLKs,
the part enters partial power-down, the conversion that was ini-
tiated by the falling edge of CS is terminated, and DOUTA and
DOUTB go back into three-state. If CS is brought high before the
second ADSCLK falling edge, the part remains in normal mode
and does not power down. This avoids accidental power-down
due to glitches on the CS line.
To exit this mode of operation and power up the ADC again, a
dummy conversion is performed. On the falling edge of CS, the
device begins to power up and continues to power up as long as
CS is held low until after the falling edge of the 10th ADSCLK.
The device is fully powered up after approximately 1 μs has
elapsed, and valid data results from the next conversion, as
shown in Figure 82 (Exiting Partial Power-Down Mode). If CS
is brought high before the second falling edge of ADSCLK, the
ADC again goes into partial power-down. This avoids acciden-
tal power-up due to glitches on the CS line. Although the device
may begin to power up on the falling edge of CS, it powers down
again on the rising edge of CS. If the ADC is already in partial
power-down mode and CS is brought high between the second
and 10th falling edges of ADSCLK, the device enters full power-
down mode.
Full Power-Down Mode
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes substan-
tially longer than that from partial power-down. This mode is
more suited to applications where a series of conversions per-
formed at a relatively high throughput rate are followed by a
long period of inactivity and thus power-down. When the ADC
is in full power-down, all analog circuitry is powered down. Full
power-down is entered in a similar way as partial power-down,
except the timing sequence shown in Figure 81 (Entering Partial
Power-Down Mode) must be executed twice. The conversion
process must be interrupted in a similar fashion by bringing CS
high anywhere after the second falling edge of ADSCLK and
before the 10th falling edge of ADSCLK. The device enters par-
tial power-down at this point. To reach full power-down, the
next conversion cycle must be interrupted in the same way, as
shown in Figure 83 (Entering Full Power-Down Mode). Once
CS is brought high in this window of ADSCLKs, the part com-
pletely powers down.
Note that it is not necessary to complete the 14 ADSCLKs once
CS is brought high to enter a power-down mode.
To exit full power-down and power up the ADC, a dummy con-
version is performed, as when powering up from partial power-
down. On the falling edge of CS, the device begins to power up
and continues to power up, as long as CS is held low until after
the falling edge of the 10th ADSCLK. The required power-up
time must elapse before a conversion can be initiated, as shown
in Figure 84 (Exiting Full Power-Down Mode). See the Power-
Up Times section for the power-up times associated with the
ADC.
Figure 81. Entering Partial Power-Down Mode
ADSCLK
THREE-STATE
CS
DOUTA
DOUTB
114
10
2
Figure 82. Exiting Partial Power-Down Mode
ADSCLK
CS
DOUTA
DOUTB
INVALID DATA
VALID DATA
110
14
1
THE PART BEGINS
TO POWER UP.
THE PART IS FULLY
POWERED UP; SEE
POWER-UP TIMES
SECTION.
tPOWER-UP1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX6519UKP055+T | IC TEMP SENSOR SW SOT23-5 |
| ADSP-BF526KBCZ-3 | IC DSP CTRLR 300MHZ 289CSPBGA |
| TRJC107K010RRJ | CAP TANT 100UF 10V 10% 2312 |
| ECM12DRKI | CONN EDGECARD 24POS DIP .156 SLD |
| ECM08DRAI | CONN EDGECARD 16POS R/A .156 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-BF504KCPZ-3F | 功能描述:IC CCD SIGNAL PROCESSOR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF504KCPZ-4 | 功能描述:IC CCD SIGNAL PROCESSOR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF504KCPZ-4F | 功能描述:IC CCD SIGNAL PROCESSOR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF506BSWZ-3F | 功能描述:IC DSP 400MHZ 1.4V 120LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF506BSWZ-4F | 功能描述:IC DSP 400MHZ 1.4V 120LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。