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| 型號： | ADV7330 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 11-Bit Triple DAC Video Encoder |
| 中文描述： | 多格式11位DAC的視頻編碼器三 |
| 文件頁數(shù)： | 23/76頁 |
| 文件大?。?/td> | 1378K |
| 代理商： | ADV7330 |
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REV. B
ADV7330
–23–
SR7–
SR0
4Ah
Register
Bit Description
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register Setting
Reset Values
SD Timing Register 0
SD Slave/Master Mode
0
1
Slave Mode
Master Mode
Mode 0
Mode 1
Mode 2
Mode 3
Enabled
Disabled
No Delay
2 Clk Cycles
4 Clk Cycles
6 Clk Cycles
– 40 IRE
– 7.5 IRE
A low-high-low transition will reset the
internal SD timing counters.
08h
SD Timing Mode
0
0
1
1
0
1
0
1
SD
BLANK
Input
0
1
SD Luma Delay
0
0
1
1
0
1
0
1
SD Min. Luma Value
0
1
0
SD Timing Reset
x
0
0
0
0
0
0
4Bh
SD Timing Register 1
SD
HSYNC
Width
0
0
1
1
0
1
0
1
T
A
= 1 Clk Cycle
T
A
= 4 Clk Cycles
T
A
= 16 Clk Cycles
T
A
= 128 Clk Cycles
T
B
= 0 Clk Cycle
T
B
= 4 Clk Cycles
T
B
= 8 Clk Cycles
T
B
= 18 Clk Cycles
T
C
= T
B
T
C
= T
B
+ 32 μs
1 Clk Cycle
4 Clk Cycles
16 Clk Cycles
128 Clk Cycles
0 Clk Cycles
1 Clk Cycle
2 Clk Cycles
3 Clk Cycles
Subcarrier Frequency Bit 7–0
Subcarrier Frequency Bit 15–8
Subcarrier Frequency Bit 23–16
Subcarrier Frequency Bit 31–24
Subcarrier Phase Bit 9–2
Extended Data Bit 7–0
Extended Data Bit 15–8
Data Bit 7–0
Data Bit 15–8
Setting any of these bits to 1
will disable pedestal on the
line number indicated by the
bit settings.
00h
SD
HSYNC
to
VSYNC
Delay
0
0
1
1
0
1
0
1
SD
HSYNC
to
VSYNC
Rising
Edge Delay (Mode 1 Only)
VSYNC
Width (Mode 2 Only)
x
x
0
0
1
1
0
1
0
1
0
1
HSYNC
to Pixel Data Adjust
0
0
1
1
x
x
x
x
x
x
x
x
x
0
1
0
1
x
x
x
x
x
x
x
x
x
16
24
16
24
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
SD F
SC
Register 0
SD F
SC
Register 1
SD F
SC
Register 2
SD F
SC
Register 3
SD F
SC
Phase
SD Closed Captioning
SD Closed Captioning
SD Closed Captioning
SD Closed Captioning
SD Pedestal Register 0
SD Pedestal Register 1
SD Pedestal Register 2
SD Pedestal Register 3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
16h
7Ch
F0h
21h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Extended Data on Even Fields
Extended Data on Even Fields
Data on Odd Fields
Data on Odd Fields
Pedestal on Odd Fields
Pedestal on Odd Fields
Pedestal on Even Fields
Pedestal on Even Fields
17
25
17
25
15
23
15
23
14
22
14
22
13
21
13
21
12
20
12
20
11
19
11
19
10
18
10
18
LINE 313
LINE 314
LINE 1
t
B
HSYNC
VSYNC
t
A
t
C
Figure 15. Timing Register 1 in PAL Mode
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